Optimization of routing layers and board space requirements for ball grid array package implementations including array corner considerations

A method for designing a land pattern that mates an integrated circuit device to a printed circuit board, the land pattern having a required number of perimeter routing channels, the method comprising the steps of:

• (a) selecting a land pattern that yields at least a required number of pads;
• (b) selecting a pad arrangement for at least one corner portion of the selected land pattern;
• (c) under populating at least one perimeter edge of the selected land pattern in a portion of the at least one perimeter edge outside of the selected pad arrangement for the at least one corner portion;
• and
• (d) after steps (b) and (c), determining whether the selected land pattern yields at least the required number of perimeter routing channels.

A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising the steps of:

• (1) determining a number of required pads;
• (2) determining a number of required perimeter routing channels;
• (3) selecting a land pattern to yield the required number of pads and number of required perimeter routing channels, wherein the land pattern is selected from a table listing optimized land patterns, wherein the table lists a number of externally available routing channels for each optimized land pattern,
• wherein the number of externally available routing channels listed in the table for each optimized land pattern includes the additional routing channels added by including at least one under populated perimeter edge in the particular optimized land pattern, and is reduced by any routing channels lost by a pad arrangment selected for at least one corner portion of the particular optimized land pattern.