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US 2004/0164425 A1Published application
Memory chip and semiconductor device using the memory chip and manufacturing method of those
AssigneeKabushiki Kaisha Toshiba
InventorYukihiro Urakawa
Life of this patent
Estimating the term…
Abstract
In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.
Claims17
A COC device comprising:
- a logic chip having a logic circuit;
- a memory chip mounted on the logic chip, the memory chip comprising:
- basic chips functioning as a chip independently from each other;
- and a dicing line interposed between the basic chips, connecting the basic chips, and configuring a part of the memory chip;
- and
- a bump connecting the logic chip and the memory chip.
3 more elements
A COC device comprising:
- a logic chip having a logic circuit;
- a memory chip mounted on the logic chip, the memory chip comprising:
- basic chips functioning as a chip independently from each other, and capable of changing a word organization by a control signal;
- and a dicing line interposed between the basic chips, connecting the basic chips, and configuring a part of the memory chip;
- and
- a bump connecting the logic chip and the memory chip;
- wherein the control signal is supplied from the logic chip to the memory chip.
4 more elements
Dependencies are inferred from the claim text.