Multilevel copper interconnects with low-k dielectrics and air gaps

A system having a multilevel wiring interconnect, comprising:

• an integrated circuit device;
• and
• an integrated memory circuit operably coupled to the integrated circuit device, wherein the integrated memory circuit includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising:
• a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;
• a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate;
• and
• wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material.

A system, comprising:

• a processor;
• and
• an integrated memory circuit coupled to the processor, wherein the integrated memory circuit further includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising:
• a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;
• a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate;
• and
• wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material.