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US 2004/0164398 A1Published application
System-on-a-chip with multi-layered metallized through-hole interconnection
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
Life of this patent
Estimating the term…
Abstract
The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips.
Claims131
A chip mounting system comprising:
- a substrate for mounting at least one chip, said substrate having at least one through-hole;
- and
- a multi-layer structure covering both sides of said substrate and passing through said at least one through-hole, said multi-layer structure comprising at least one conductive plane and a signal wiring layer, said at least one conductive plane and said signal wiring layer having an insulating layer interposed between them.
A chip mounting system comprising:
- a substrate for mounting at least one chip, said substrate having at least one through-hole;
- a multi-layer structure covering both sides of said substrate and passing through said through-hole, said multi-layer structure comprising a conductive plane and a signal wiring layer having traces terminating in bond pads, said conductive plane and said signal wiring layer having an insulating layer interposed between them;
- and
- said at least one chip mounted onto said bond pads.
1 more element
The chip mounting system of claim 34, wherein said first ground plane is at least 3 μm thick.
A processor system comprising:
- a processor;
- and
- memory device coupled to said processor, said processor and memory device residing on a common substrate, said substrate having a through-hole, said substrate further comprising a top side and a bottom side with multi-layer structure interposed on both sides of said substrate and passing through said through-hole, said multi-layer structure comprising:
- a conductive plane;
- and
- a signal wiring layer, said conductive plane and said signal wiring layer having an insulating layer interposed between them.
3 more elements
A integrated circuit package comprising:
- a substrate for mounting at least one chip, said substrate having at least one through-hole;
- a multi-layer structure covering both sides of said substrate and passing through said through-hole, said multi-layer structure comprising a conductive plane and a signal wiring layer, said conductive plane and said signal wiring layer having an insulating layer interposed between them;
- and
- a integrated circuit package to encase said substrate, said multi-layer structure and at least one circuit chip.
1 more element
A method of forming a chip carrier, said method comprising:
- forming a conductive plane on both sides of a substrate and in at least one through-hole of said substrate;
- forming at least one insulating layer over said conductive plane and in at least one through-hole of said substrate;
- and
- forming a signal wiring layer over said at least one insulating layer and in at least one through-hole of said substrate.
1 more element
A method of forming a chip carrier, said method comprising:
- forming a first insulating layer on both sides of a substrate and in at least one through-hole of said substrate;
- forming a conductive plane over said first insulating layer and in at least one through-hole of said substrate;
- forming a second insulating layer over said conductive plane and in at least one through-hole of said substrate;
- and
- forming a signal wiring layer over said second insulating layer and in at least one through-hole of said substrate.
2 more elements
A method of forming a chip carrier, said method comprising:
- forming a first insulating layer on both sides of a substrate and in at least one through-hole of said substrate;
- forming a first conductive plane over said first insulating layer and in at least one through-hole of said substrate;
- forming a second insulating layer over said first conductive plane and in at least one through-hole of said substrate;
- fabricating signal lines over said second insulating layer and in at least one through-hole of said substrate;
- forming a third insulating layer over said signal lines and in at least one through-hole of said substrate;
- forming a second conductive plane over said third insulating layer and in at least one through-hole of said substrate;
- forming a fourth insulating layer over said second conductive plane and in at least one through-hole of said substrate;
- and
- mounting a plurality of integrated circuit chips over said fourth insulating layer.
6 more elements
Dependencies are inferred from the claim text.