Stacked semiconductor package and method for fabricating
AssigneeSamsung Electronics Co., Ltd.
InventorChan-Suk Lee
Life of this patent
Estimating the term…
Abstract
In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.
Claims22
A stacked semiconductor package comprising:
- a first semiconductor chip;
- a second semiconductor chip stacked offset over the first semiconductor chip such that a portion of the first semiconductor chip is exposed;
- and
- at least one first conductor electrically connecting the exposed portion of the first semiconductor chip to the second semiconductor chip, the first conductor not extending beyond a periphery of the first semiconductor chip.
12 The package of claim 11, wherein the frame is one of a printed circuit board and a flexible substrate.
A stacked semiconductor package comprising:
- a stacked chip structure including an upper semiconductor chip and at least one lower semiconductor chip disposed under at least a portion of the upper semiconductor chip;
- and
- a redistribution pattern redistributing a first plurality of bond pads on the upper semiconductor chip to a differently positioned second plurality of bond pads on the upper semiconductor chip, the first plurality of bond pads being electrically connected with the lower semiconductor chip.
A method for fabricating a stacked semiconductor package, comprising:
- forming a stacked chip package including at least a first semiconductor chip and a second semiconductor chip stacked offset over the first semiconductor chip such that a portion of the first semiconductor chip is exposed;
- and
- electrically connecting the exposed portion of the first semiconductor chip to the second semiconductor chip using at least one conductor such that the conductor does not extend beyond a periphery of the first semiconductor chip.
A method for fabricating a stacked semiconductor package, comprising:
- forming a stacked chip structure including an upper semiconductor chip and at least one lower semiconductor chip disposed under at least a portion of the upper semiconductor chip;
- and
- electrically connecting the lower semiconductor chip with a first plurality of bond pads on the upper semiconductor chip;
- and
- forming a redistribution pattern redistributing the first plurality of bond pads on the upper semiconductor chip to a differently positioned second plurality of bond pads on the upper semiconductor chip.
Dependencies are inferred from the claim text.