US 2004/0164385 A1 · Semiconductor device and manufacturing method thereof

Abstract

Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Claims37

Dependent claims

A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a wiring substrate having a plurality of wiring lines over a main surface thereof;
(b) providing a first semiconductor chip and a second semiconductor chip each having over a main surface thereof a plurality of semiconductor elements and a plurality of electrodes;
(c) mounting the first semiconductor chip over the main surface of the wiring substrate through a plurality of first bump electrodes in such a manner that the main surface thereof is opposed to the main surface of the wiring substrate;
(d) mounting the second semiconductor chip over the main surface of the wiring substrate through a plurality of second bump electrodes in such a manner that the main surface thereof is opposed to the main surface of the wiring substrate and that one side faces of the first and the second semiconductor chips are adjacent to each other;
(e) filling an area with a first resin which area is defined by the adjacent one side faces of the first and the second semiconductor chips and the main surface of the wiring substrate;
and
(f) after the step (e), sealing the first and the second semiconductor chips with a second resin.

4 more elements

A semiconductor device comprising:

(a) a wiring substrate of a square shape having, over a main surface thereof, a plurality of wiring lines and a plurality of electrode pads;
(b) a first semiconductor chip of a square shape having, over a main surface thereof, a plurality of semiconductor elements and a plurality of electrodes, the first semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of first bump electrodes in such a manner that the main surface thereof is opposed to the main surface of the wiring substrate;
(c) a second semiconductor chip of a square shape having, over a main surface thereof, a plurality of semiconductor elements and a plurality of electrodes, the second semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of second bump electrodes in such a manner that the main surface thereof is opposed to the main surface of the wiring substrate and that one side face thereof and one side face of the first semiconductor chip are adjacent to each other;
(d) a third semiconductor chip having, over a main surface thereof, a plurality of semiconductor elements and a plurality of electrodes, the third semiconductor chip being stacked over the first and the second semiconductor chips in such a manner that a back side thereof is opposed to back sides of the first and the second semiconductor chips;
(e) a plurality of bonding wires for electrically connecting the plural electrode pads of the wiring substrate and the plural electrodes of the third semiconductor chip with each other;
and
(f) a resin member for sealing the first, second and third semiconductor chips and the plural bonding wires,
wherein the plural electrode pads of the wiring substrate is disposed between the first semiconductor chip and a first side of the wiring substrate and also between the second semiconductor chip and a second side of the wiring substrate opposed to the first side, and
wherein the distance between one mutually adjacent side faces of the first and the second semiconductor chips is shorter than the distance between the first semiconductor chip and the first side of the wiring substrate and the distance between the second semiconductor chip and the second side of the wiring substrate.

6 more elements

A semiconductor device comprising:

(a) a wiring substrate having over a main surface thereof a plurality of wiring lines and a plurality of electrode pads;
(b) a first semiconductor chip having, over a main surface thereof, a plurality of semiconductor elements and a plurality of electrodes, the first semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of bump electrodes in such a manner that a main surface thereof is opposed to the main surface of the wiring substrate;
(c) a second semiconductor chip having over a main surface thereof a plurality of semiconductor elements and a plurality of electrodes, the second semiconductor chip being stacked over the first semiconductor chip in such a manner that a back side thereof is opposed to a back side of the first semiconductor chip;
(d) a plurality of bonding wires for electrically connecting the plural electrode pads of the wiring substrate and the plural electrodes of the second semiconductor chip with each other;
and
(e) a resin member for sealing the first and the second semiconductor chips and the plural bonding wires,
wherein the pitch between the plural bump electrodes is larger than that between the plural electrodes of the second semiconductor chip.

4 more elements

A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a multi-wiring substrate, a first semiconductor chip having a plurality of first bump electrodes over a main surface thereof, a second semiconductor chip having a plurality of second bump electrodes over a main surface thereof, and a third semiconductor chip, the multi-wiring substrate having a main surface partitioned into a plurality of wiring substrate-forming areas, with a plurality of wiring lines and a plurality of electrode pads being formed in each of the plural wiring substrate-forming areas;
(b) disposing the first semiconductor chip in each of first areas in the plural wiring substrate-forming areas in such a manner that the main surface thereof is opposed to the main surface of the multi-wiring substrate, disposing the second semiconductor chip in each of second areas in the plural wiring substrate-forming areas in such a manner that the main surface thereof is opposed to the main surface of the multi-wiring substrate, thereby electrically connecting the first semiconductor chip and the wiring lines of the multi-wiring substrate with each other through the plural first bump electrodes, and electrically connecting the second semiconductor chip and the wiring lines of the multi-wiring substrate with each other through the plural second bump electrodes;
(c) injecting a first resin into a gap between the first and the second semiconductor chips and the multi-wiring substrate and also into a gap between the first and the second semiconductor chips;
(d) stacking the third semiconductor chip over the first and the second semiconductor chips in such a manner that a back side thereof is opposed to the first and the second semiconductor chips, and thereafter electrically connecting the third semiconductor chip and the electrode pads of the multi-wiring substrate with each other through a plurality of wires;
(e) sealing the first, second and third semiconductor chips mounted over the main surface of the multi-wiring substrate with a second sealing resin;
and
(f) dicing the multi-wiring substrate along boundary portions of the plural wiring substrate-forming areas to afford wiring substrates, each of the wiring substrates having the first, second and third semiconductor chips mounted over a main surface thereof.

4 more elements

A semiconductor device comprising:

(a) a wiring substrate having, over a main surface thereof, a plurality of wiring lines and a plurality of electrode pads;
(b) a first semiconductor chip having, over a mains surface thereof, a plurality of semiconductor elements and a plurality of electrodes, the first semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of bump electrodes in such a manner that the main surface thereof is opposed to the main surface of the wiring substrate;
(c) a second semiconductor chip having, over a main surface thereof, a plurality of semiconductor elements and a plurality of electrodes, the second semiconductor chip being stacked over the first semiconductor chip in such a manner that a back side thereof is opposed to a back side of the first semiconductor chip;
(d) a plurality of bonding wires for electrically connecting the plural electrode pads of the wiring substrate and the plural electrodes of the second semiconductor chip with each other;
and
(e) a resin member for sealing the first and the second semiconductor chips and the plural bonding wires,
wherein the wiring substrate further has a first area in which a plurality of address terminals are mainly concentrated and a second area adjacent to the first area and in which a plurality of data terminals are mainly concentrated,
wherein on one end side of the main surface of the first semiconductor chip are mainly concentrated a plurality of address terminals, while on an opposite end side of the main surface of the first semiconductor chip are mainly concentrated a plurality of data terminals, and
wherein the first semiconductor chip mounted over the main surface of the wiring substrate is oriented so that one end side of the first semiconductor chip with the plural address terminals concentrated thereon and the first area of the wiring substrate with the plural address terminals concentrated therein are in proximity to each other, and the opposite end side of the first semiconductor chip with the plural data terminals concentrated thereon and the second area of the wiring substrate with the plural data terminals concentrated therein are in proximity to each other.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor device and manufacturing method thereof

Life of this patent

Semiconductor device and manufacturing method thereof

Life of this patent

Abstract

Claims37