Lanthanide doped TiOx dielectric films
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
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Abstract
A dielectric film containing lanthamide doped TiOx and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric film is formed by ion assisted electron beam evaporation of TiO2 and electron beam evaporation of a lanthamide selected from a group consisting of Nd, Tb, and Dy. The growth rate is controlled to provide a dielectric film having a lanthamide content ranging from about ten to about thirty percent of the dielectric film. These dielectric films containing lanthamide doped TiOx are amorphous and thermodynamically stable such that the lanthamide doped TiOx will have minimal reactions with a silicon substrate or other structures during processing.
Claims40
An electronic device comprising:
- a substrate;
- and
- a dielectric layer disposed on the substrate, the dielectric layer containing a TiOx layer doped with a lanthamide, wherein the TiOx layer is formed by ion assisted electron beam evaporation.
An electronic device comprising:
- a substrate;
- and
- a dielectric layer disposed on the substrate, the dielectric layer containing a TiOx layer doped with Nd, wherein the TiOx layer is formed by ion assisted electron beam evaporation.
An electronic device comprising:
- a substrate;
- and
- a dielectric layer disposed on the substrate, the dielectric layer containing a TiOx layer doped with Th, wherein the TiOx layer is formed by ion assisted electron beam evaporation.
An electronic device comprising:
- a substrate;
- and
- a dielectric layer disposed on the substrate, the dielectric layer containing a TiOx layer doped with Dy, wherein the TiOx layer is formed by ion assisted electron beam evaporation.
A transistor comprising:
- a source region disposed in a substrate;
- a drain region disposed in the substrate;
- a body region located between the source region and the drain region;
- a dielectric layer disposed on the body region between the source region and the drain region, the dielectric layer containing a TiOx layer doped with a lanthamide, wherein the TiOx layer is formed by ion assisted electron beam evaporation;
- and
- a gate coupled to the dielectric layer.
A capacitor comprising:
- a first conductive layer disposed on a substrate;
- a dielectric layer disposed on the first conductive layer, the dielectric layer containing a TiOx layer doped with a lanthamide, wherein the TiOx layer is formed by ion assisted electron beam evaporation;
- and
- a second conductive layer disposed on the dielectric layer.
A memory comprising:
- a number of access transistors, each access transistor having a source region disposed in a substrate, a drain region disposed in the substrate, and a gate, at least one access transistor including a dielectric layer disposed on the substrate with the gate disposed on the dielectric layer, the dielectric layer containing a TiOx layer doped with a lanthamide, wherein the TiOx layer is formed by ion assisted electron beam evaporation;
- a number of word lines coupled to a number of the gates of the number of access transistors;
- a number of source lines coupled to a number of the source regions of the number of access transistors;
- and
- a number of bit lines coupled to a number of the drain regions of the number of access transistors.
An electronic system, comprising:
- a processor;
- a system bus;
- and
- a memory array coupled to the processor by the system bus, the memory array including:
- a number of access transistors, each access transistor having a source region disposed in a substrate, a drain region disposed in the substrate, and a gate, at least one access transistor including a dielectric layer disposed on the substrate with the gate disposed on the dielectric layer, the dielectric layer containing a TiOx layer doped with a lanthamide, wherein the TiOx layer is formed by ion assisted electron beam evaporation;
- a number of word lines coupled to a number of the gates of the number of access transistors;
- a number of source lines coupled to a number of the source regions of the number of access transistors;
- and
- a number of bit lines coupled to a number of the drain regions of the number of access transistors.
Dependencies are inferred from the claim text.