Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
AssigneeHRL Laboratories, LLC
InventorsJames P. Baukus, Lap-Wai Chow, William M. Clark JR.
Life of this patent
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Abstract
A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.
Claims17
A permanently-ON MOS transistor (21) comprising:
- a silicon source region (9′) of a first conductivity type;
- a silicon drain region (9′) of the first conductivity type;
- a silicon well region (3) of a second conductivity type, in which said source region and drain region are buried;
- a silicon contact region (15) of the first conductivity type, buried in the well region (3), said contact region (15) contacting said source region (9′) and said drain region (9′);
- a first gate insulating layer (2) selectively placed over the silicon source region (9′) and the silicon drain region (9′);
- a second gate insulating layer (7) selectively placed over the first gate insulating layer (2) and over the silicon contact region (15);
- and
- a polysilicon gate region (8′) placed over the second gate insulating layer (7).
An integrated circuit structure for MOS-type devices comprising at least one permanently-ON MOS transistor (21), said transistor including:
- a first silicon source region (9′) of a first conductivity type;
- a first silicon drain region (9′) of the first conductivity type;
- a first silicon well region (3) of a second conductivity type, in which the first silicon source region (9′) and the first silicon drain region (9′) are buried;
- a silicon contact region (15) of the first conductivity type, buried in the well region (3), the contact region (15) contacting the silicon source region (9′) and the silicon drain region (9′);
- a first gate insulating layer (2) selectively placed over the silicon source region (9′) and the silicon drain region (9′);
- a second gate insulating layer (7) selectively placed over the first gate insulating layer (2) and over the silicon contact region (15);
- and
- a first polysilicon gate region (8′) placed over the second gate insulating layer (7).
A process for forming a permanently-ON MOS transistor (21) comprising the steps of:
- providing a silicon well region (3) of a first conductivity type;
- depositing a first insulating layer (2) over the silicon well region (3) of the first conductivity type;
- removing a portion of said deposited first insulating layer;
- forming a buried silicon region (15) of a second conductivity type within the silicon well region (3) of the first conductivity type, under the removed portion of said deposited first insulating layer;
- depositing a second insulating layer (7) over the first insulating layer (2) and over the buried silicon region (15) of the second conductivity type;
- forming a polysilicon gate region (8′) over the second insulating layer;
- and
- forming a source region (9′) of the second conductivity type and a drain region (9′) of the second conductivity type within the buried silicon well region (3), said source region and drain region contacting said buried silicon region (15) of the second conductivity type.
Dependencies are inferred from the claim text.