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US 2004/0164360 A1Published application
Semiconductor integrated circuit device and a method of manufacturing the same
AssigneeRenesas Technology Corp.
InventorsAkio Nishida, Hiraku Chakihara, Koichi Toba
Life of this patent
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Abstract
An object is to improve soft error resistance of the memory cell of an SRAM without increasing its chip size. In deep through-holes formed by perforating a silicon oxide film, a silicon nitride film and a silicon oxide film, a capacitor element having a TiN film as a lower electrode, a silicon nitride film as an insulator and a TiN film as an upper electrode. This capacitor element is connected between a storage node and a supply voltage line, between a storage node and a reference voltage line, or between storage nodes of the memory cell of the SRAM.
Claims22
A semiconductor integrated circuit device comprising:
- a memory cell having first and second transfer MISFETs, first and second drive MISFETs and first and second load MISFETs, each disposed at an intersection between a pair of complementary data lines and a word line, the first drive MISFET and first load MISFET being cross-coupled with the second drive MISFET and second load MISFET,
- wherein the first and second transfer MISFETs and the first and second drive MISFETs are formed over the main surface of a semiconductor substrate,
- wherein a first insulating film is formed over the semiconductor substrate and a first opening is formed in the first insulating film,
- wherein a first capacitor element is formed over the sidewall and bottom of the first opening, the first capacitor element having, as a lower electrode, a first conductive film formed along the sidewall and bottom of the first opening, as a capacitor insulator film, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film,
- wherein a supply voltage line electrically connected to the first and second drive MISFETs and a reference voltage line electrically connected to the first and second drive MISFETs are formed over the first capacitor element,
- wherein the lower electrode forms a first storage node of the memory cell by electrically connecting a drain of the first drive MISFET, a drain of the first load MISFET, a gate electrode of the second drive MISFET and a gate electrode of the second load MISFET, and a second storage node of the memory cell by electrically connecting a drain of the second drive MISFET, a drain of the second load MISFET, a gate electrode of the first drive MISFET and a gate electrode of the first load MISFET, and
- wherein the first capacitor element is electrically connected between the first storage node and second storage node, and the supply voltage line, between the first storage node and second storage node, and the reference voltage line, or between the first storage node and the second storage node.
4 more elements
A semiconductor integrated circuit device comprising:
- a memory cell having first and second transfer MISFETS, first and second drive MISFETs and first, and second load MISFETS, each disposed at an intersection between a pair of complementary data lines and a word line, the first drive MISFET and first load MISFET being cross-coupled with the second drive MISFET and second load MISFET;
- and
- a power supply circuit,
- wherein the memory cell is formed in a first region over the main surface of the semiconductor substrate and the power supply circuit is formed in a second region over the main surface of the semiconductor substrate,
- wherein a first insulating film is formed over the semiconductor substrate,
- wherein in a second opening formed in the first insulating film in the second region, a second capacitor element having, as a lower electrode, a first conductive film formed along the sidewall and bottom of the second opening, as an insulator, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film, and
- wherein the power supply circuit feeds the memory cell with an operating voltage and the second capacitor element is electrically connected between the operating voltage and ground voltage.
4 more elements
A semiconductor integrated circuit device, comprising a first insulating film formed over a semiconductor substrate, a second opening formed in the first insulating film, and a capacitor element having, as a lower electrode, a first conductive film formed along the sidewall and bottom of the second opening, as a capacitor insulator film, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film formed over the sidewall and the bottom of the second opening, said capacitor element constituting an analog circuit.
A manufacturing method of a semiconductor integrated circuit device, comprising:
- a memory cell having first and second transfer MISFETs, first and second drive MISFETs and first and second load MISFETs, each disposed at the intersection between a pair of complementary data lines and a word line, the first drive MISFET and first load MISFET being cross-coupled with the second drive MISFET and second load MISFET,
- the method comprising the steps of:
- (a) forming the first and second transfer MISFETs and the first and second drive MISFETs over the main surface of a semiconductor substrate;
- (b) forming a first insulating film over the semiconductor substrate and making a first opening in the first insulating film;
- (c) forming a first conductive film over the sidewall and bottom of the first opening, forming a first storage node of the memory cell by electrically connecting, via the first conductive film, a drain of the first drive MISFET, a drain of the first load MISFET, a gate electrode of the second drive MISFET and a gate electrode of the second load MISFET, and forming a second storage node by electrically connecting, via the first conductive film, a drain of the second drive MISFET, a drain of the second load MISFET, a gate electrode of the first drive MISFET and a gate electrode of the first load MISFET;
- (d) forming a second insulating film over the first conductive film, forming a second conductive film over the second insulating film, and forming a first capacitor element having the first conductive film as a lower electrode, the second insulating film as a capacitor insulator film and the second conductive film as an upper electrode;
- and
- (e) forming a supply voltage line and a reference voltage line over the first capacitor element, said first capacitor element being electrically connected between the first storage node and second storage node, and the supply voltage line, between the first storage node and second storage node, and the reference voltage line, or between the first storage node and the second storage node.
5 more elements
A manufacturing method of a semiconductor integrated circuit device comprising:
- a memory cell having first and second transfer MISFETs, first and second drive MISFETs and first and second load MISFETs, each disposed at an intersection between a pair of complementary data lines and a word line, the first drive MISFET and first load MISFET being cross-coupled with the second drive MISFET and second load MISFET;
- and
- a power supply circuit for feeding the memory cell with an operating voltage,
- wherein the memory cell is formed in a first region over the main surface of the semiconductor substrate and the power supply circuit is formed in a second region over the main surface of the semiconductor substrate,
- the method comprising the steps of:
- (a) forming a first insulating film over the semiconductor substrate;
- (b) making a second opening in the first insulating film in the second region;
- and
- (c) forming a first conductive film over the sidewall and bottom of the second opening, a second insulating film over the first conductive film, a second conductive film over the second insulating film, and a second capacitor element which has the first conductive film as a lower electrode, the second insulating film as a capacitor insulator film and the second conductive film as an upper electrode and is electrically connected between the operating voltage and ground potential.
6 more elements
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
- (a) forming a first insulating film over a semiconductor substrate;
- (b) forming a second opening in the first insulating film;
- and
- (c) forming a first conductive film along the sidewall and bottom of the second opening, a second insulating film over the first conductive film, a second conductive film over the second insulating film and a capacitor element having the first conductive film as a lower electrode, the second insulating film as an insulator and the second conductive film as an upper electrode,
- wherein an analog circuit is formed using the capacitor element.
2 more elements
A semiconductor integrated circuit device comprising:
- a first insulating film formed over a semiconductor substrate;
- and
- a plurality of second openings formed in the first insulating film,
- wherein a capacitor element is formed over the sidewall and bottom of the plurality of second openings and has, as a lower electrode, a first conductive film formed along the sidewall and bottom of the second openings, as an insulator, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film in the plurality of second openings.
1 more element
Dependencies are inferred from the claim text.