Atomic layer-deposited LaAIO3 films for gate dielectrics

A transistor comprising:

• a body region between first and second source/drain regions in a substrate;
• a film on the body region between the first and second source/drain regions, the film containing LaAlO3;
• and
• a gate coupled to the film;
• the film being formed by atomic layer deposition including:
• pulsing a lanthanum containing precursor into a reaction chamber containing a substrate;
• pulsing a first oxygen containing precursor into the reaction chamber;
• pulsing an aluminum containing precursor into a reaction chamber;
• and
• pulsing a second oxygen containing precursor into the reaction chamber.

A transistor comprising:

• a body region between first and second source/drain regions in a substrate;
• a film on the body region between the first and second source/drain regions, the film containing atomic layer deposited LaAlO3;
• and
• a gate coupled to the film.

A memory comprising:

• a number of access transistors, each access transistor including:
• a body region between first and second source/drain regions in a substrate;
• a film on the body region between the first and second source/drain regions, the film containing LaAlO3;
• and
• a gate coupled to the film;
• a number of word lines coupled to a number of the gates of the number of access transistors;
• a number of source lines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• a number of bit lines coupled to a number of the second source/drain regions of
• the number of access transistors;
• the film being formed by atomic layer deposition including:
• pulsing a lanthanum containing source gas into a reaction chamber containing a substrate;
• pulsing an aluminum containing source gas into a reaction chamber.

A memory comprising:

• a number of access transistors, each access transistor including:
• a body region between first and second source/drain regions in a substrate;
• a film on the body region between the first and second source/drain regions, the film containing atomic layer deposited LaAlO3;
• and
• a gate coupled to the film;
• a number of word lines coupled to a number of the gates of the number of access transistors;
• a number of source lines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors.

An information handling device comprising:

• a processor;
• a memory, the memory including:
• a number of access transistors, each access transistor having:
• first and second source/drain regions in a substrate;
• a body region between the first and second source/drain regions;
• a film on the body region between the first and second source/drain regions, the film containing LaAlO3;
• and
• a gate coupled to the film;
• a number of word lines coupled to a number of the gates of the number of
• access transistors;
• a number of source lines coupled to a number of the first source/drain regions
• of the number of access transistors;
• a number of bit lines coupled to a number of the second source/drain regions
• of the number of access transistors;
• and
• a system bus that couples the processor to the memory array;
• the film being formed by atomic layer deposition including:
• pulsing a lanthanum containing source gas into a reaction chamber containing the substrate;
• and
• pulsing an aluminum containing source gas into the reaction chamber.

An information handling device comprising:

• a processor;
• a memory, the memory including:
• a number of access transistors, each access transistor having:
• first and second source/drain regions in a substrate;
• a body region between the first and second source/drain regions;
• a film on the body region between the first and second source/drain regions, the film containing atomic layer deposited LaAlO3;
• and
• a gate coupled to the film;
• a number of word lines coupled to a number of the gates of the number of
• access transistors;
• a number of source lines coupled to a number of the first source/drain regions
• of the number of access transistors;
• and
• a number of bit lines coupled to a number of the second source/drain regions
• of the number of access transistors;
• and
• a system bus that couples the processor to the memory array.