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AssigneeSarnoff Corporation
InventorsMarkus Paul Josef Mergens, Koen Gerard Maria Verhaege, Cornelius Christian Russ, John Armer, Phillip Czeslaw Jozwiak, Bart Keppens
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An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, said MOS transistor formed in an I/O periphery of an integrated circuit (IC) for providing ESD protection for said IC, said MOS transistor comprising:
An electrostatic discharge (ESD) PMOS transistor including a plurality of interleaved fingers, said MOS transistor formed in an I/O periphery of an integrated circuit (IC) for providing ESD protection for said IC, said MOS transistor comprising:
An electrostatic discharge (ESD) MOS transistor formed in an I/O periphery of an integrated circuit (IC) for providing ESD protection for said IC, said MOS transistor comprising:
Dependencies are inferred from the claim text.