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US 2004/0164346 A1Published application
Power switching transistor with low drain to gate capacitance
AssigneeSemiconductor Components Industries, LLC
InventorPrasad Venkatraman
Life of this patent
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Abstract
A transistor (10) is formed on a semiconductor substrate (12) with a first surface (19) for forming a channel (40) to control a channel current (IDS) A gate electrode (25) is formed over first and second sections of the channel, and a drain region (13, 14, 21) extending from the top surface to a bottom surface (18) of the substrate is formed with a recessed region (30) between the first and second sections of the channel for disposing a dielectric film (20).
Claims19
A transistor, comprising:
- a semiconductor substrate having a top surface for forming a channel to control a channel current;
- a gate electrode formed over first and second sections of the channel;
- and
- a drain region extending from the top surface to a bottom surface of the semiconductor substrate, and formed with a recessed region between the first and second portions of the channel for disposing a dielectric film.
1 more element
A semiconductor device, comprising:
- a semiconductor substrate having first and second surfaces;
- a well region formed in the semiconductor substrate to provide a channel at the first surface;
- a gate electrode formed over first and second portions of the channel;
- a drain region extending between the first and second surfaces for electrically coupling to the channel;
- and
- a dielectric region formed in a recessed portion of the drain region between the first and second portions of the channel.
3 more elements
Dependencies are inferred from the claim text.