Semiconductor memory with vertical charge-trapping memory cells and fabrication

A semiconductor memory with vertical charge-trapping memory cells, the semiconductor memory comprising:

• a plurality of parallel trenches arranged at intervals to each other with corresponding walls and floors formed on a surface of a semiconductor body;
• a plurality of memory transistors in a memory cell field on the surface of the semiconductor body, each memory transistor having on one wall of one of the trenches a channel region, which is separated from a gate electrode arranged in the trench by a gate dielectric, the channel region limited by doped regions, which are adjacent to the trench at the floor of the associated trench and at the surface of the semiconductor body and which are provided as source/drain regions;
• a dielectric memory layer sequence disposed at least between an appropriate gate electrode and a source-side or a drain-side end of an associated channel region, the dielectric memory layer sequence being made from a first limiting layer, a memory layer, and a second limiting layer, the dielectric memory layer sequence being provided for programming by trapping hot electrons from the channel region;
• upper bit lines running parallel to the trenches, wherein the source/drain regions are coupled to each other at the surface of the semiconductor body between two adjacent trenches by the upper bit lines;
• and
• lower bit lines formed as doped regions in the semiconductor body, wherein the source/drain regions are connected to each other at the floors of the trenches along the same trench by the lower bit lines;
• wherein the trenches are alternating isolation trenches and active trenches, wherein the isolation trenches are also present between the lower bit lines and the active trenches are provided for the memory transistors, and outside the memory cell field there are bit-line contacts on the upper bit lines and other bit-line contacts are provided on the lower bit lines and are connected in an electrically conductive way to a metallization layer provided for wiring, wherein the bit-line contacts and the other bit-line contacts are mounted on opposite sides of the memory cell field and portions of the isolation trenches are arranged between the other bit-line contacts.

A method of forming a semiconductor device, the method comprising:

• forming a plurality of trenches in a semiconductor body, wherein the trenches alternate between active trenches and isolation trenches, the isolation trenches being deeper than the active trenches;
• doping the semiconductor body so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped;
• forming memory cell components in each active trench, the memory cell components comprising a gate electrode and a charge trapping layer disposed between the gate electrode and a sidewall of the trench, wherein the charge trapping layer comprises a memory layer disposed between first and second limiting layers;
• forming bitlines over the semiconductor body and electrically coupling doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches;
• and
• forming bitline contacts coupled to the bitlines.

A method for fabricating a semiconductor memory with vertical charge-trapping memory cells, the method comprising:

• in a first step, a hard mask layer is deposited on a surface of a semiconductor body and a photoresist layer is deposited on this mask layer;
• in a second step, the photoresist layer is provided with a plurality of parallel, strip-like openings arranged at intervals to each other under the use of a first lithography mask, the first lithography mask being formed so that the photoresist layer covers regions on a first side adjacent to a provided memory cell field, which are provided for attachment of bit-line contacts;
• in a third step, the hard mask layer is structured under the use of the photoresist layer;
• in a fourth step, the photoresist layer is replaced by a full-surface, additional photoresist layer;
• in a fifth step, the additional photoresist layer is structured under the use of a second lithography mask so that in the series of strip-like openings formed in the hard mask layer, every second opening is exposed so that remaining openings remain covered by the additional photoresist layer, wherein the second lithography mask is formed so that the additional photoresist layer covers regions on a second side that is opposite the first side adjacent to the provided memory cell field, where these regions are provided for attaching additional bit-line contacts;
• in a sixth step, under the use of the hard mask layer and the additional photoresist layer as a mask, a material present under the hard mask layer is removed in the region of the exposed openings in a direction perpendicular to the hard mask layer;
• in a seventh step, the additional photoresist layer is removed and additional material is removed in the region of the openings of the hard mask layer in a direction perpendicular to the hard mask layer in order to fabricate trenches;
• in an eighth step, the trenches produced in the seventh step are filled with an oxide and the hard mask layer is removed;
• in a ninth step, another photoresist layer is deposited and is structured under the use of a third lithography mask, wherein openings are generated above the trenches in corresponding regions, which remain covered by the photoresist layer structured in the fifth step, wherein the third lithography mask is formed so that the openings of the additional photoresist layer expose regions extending over the regions of the trenches on the second side adjacent to the provided memory cell field, which are provided for the additional bit-line contacts;
• and
• in a tenth step, under the use of the photoresist layer structured in the ninth step the oxide is removed from the corresponding trenches, which are provided for the memory transistors.