Integrated circuit memory device and method

A vertical DEAPROM memory cell, comprising:

• a first source/drain region formed on a substrate;
• a body region including a channel region formed on the first source/drain region;
• a second source/drain region formed on the body region;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate;
• and
• wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms.

A DEAPROM memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide;
• a first metal layer formed on the polysilicon floating gate;
• a metal oxide intergate insulator formed on the metal layer, wherein the metal oxide intergate insulator has a tunnel barrier of less than 1.5 eV;
• a second metal layer formed on the metal oxide intergate insulator;
• and
• a polysilicon control gate formed on the second metal layer.

A method of forming a floating gate transistor, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• forming a floating gate opposing the channel region and separated therefrom by a gate oxide;
• forming a control gate opposing the floating gate;
• and
• forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate, wherein forming the low tunnel barrier intergate insulator includes a tunnel barrier of less than 1.5 eV.

A method for operating a DEAPROM memory cell, comprising:

• writing to a floating gate of the DEAPROM memory cell using channel hot electron injection, wherein the DEAPROM memory cell includes:
• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate;
• and
• wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV;
• erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate by applying an electric field across the intergate insulator of 2.5×106 V/cm.

A method for operating an array of DEAPROM memory cells, comprising:

• writing to one or more floating gates for a number of DEAPROM memory cells in the array of DEAPROM memory cells by tunneling electrons from a control gate through a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV to a floating gate, wherein the array of DEAPROM memory cells includes:
• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells;
• and
• erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates through the low tunnel barrier intergate insulator.