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US 2004/0164341 A1Published application
Operating a memory device
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Joseph E. Geusic
Life of this patent
Estimating the term…
Abstract
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.
Claims59
A method of operating an electronic device comprising:
- storing data by changing charge on a storage electrode configured such that an energy barrier at an interface between the storage electrode and an adjacent insulator has a barrier energy of less than approximately 3.3 eV, the storage electrode having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
A method of operating an electronic device comprising:
- storing data by changing charge on a floating gate of a floating gate transistor configured such that an energy barrier at an interface between the floating gate and a gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 3.3 eV, the floating gate having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
A method of operating a memory comprising:
- activating a floating gate transistor, the floating gate transistor including a floating gate having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV, the floating gate transistor configured such that an energy barrier at an interface between the floating gate and a gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 3.3 eV, the method including:
- providing a control voltage to a control gate of the floating gate transistor to store data by changing charge on the floating gate;
- detecting a current between a drain of the floating gate transistor and a source of the floating gate transistor at a data line coupled to the drain;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
2 more elements
A method of operating a memory comprising:
- activating a floating gate transistor, the floating gate transistor including a floating gate having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV, the floating gate transistor configured such that an energy barrier at an interface between the floating gate and a gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 2.8 eV, the method including:
- providing a control voltage to a control gate of the floating gate transistor to store data by changing charge on the floating gate;
- detecting a current between a drain of the floating gate transistor and a source of the floating gate at a data line coupled to the drain;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
2 more elements
A method of operating a memory comprising:
- storing data by changing charge on a floating gate of a floating gate transistor, the floating gate transistor configured such that an energy barrier at an interface between the floating gate and a gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 1.8 eV, the floating gate having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
A method of operating a memory comprising:
- storing data by changing charge on a floating gate of a floating gate transistor, the floating gate transistor configured such that an energy barrier at an interface between the floating gate and a gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 0.8 eV, the floating gate having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
A method of operating an electronic system comprising:
- sending an address from a processor to a memory;
- sending data to the memory under the control of the processor;
- storing data in one or more memory cells of the memory, storing data in each memory cell including changing charge on a floating gate of a floating gate transistor in each memory cell, the floating gate transistor configured such that an energy barrier at an interface between the floating gate and a gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 3.3 eV, the floating gate having an electron affinity smaller than an electron affinity of polysilicon, the electron affinity of polysilicon being approximately 4.2 eV;
- and
- refreshing data based on a data charge retention time that depends upon the barrier energy.
2 more elements
Dependencies are inferred from the claim text.