Nonvolatile semiconductor memory device including improved gate electrode
AssigneeKabushiki Kaisha Toshiba
InventorsFumitaka Arai, Yasuhiko Matsunaga, Makoto Sakuma, Riichiro Shirota, Akira Shimizu
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Abstract
A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.
Claims39
A nonvolatile semiconductor memory device comprising:
- a floating gate formed on a semiconductor substrate via a gate insulating film;
- diffused layers, as sources or drain regions, which are positioned on opposite sides of the floating gate and which are formed in the semiconductor substrate;
- first and second control gates which are formed on the opposite sides of the floating gate and which drive the floating gate;
- and
- an inter-gate insulating film which insulates the first and second control gates from the floating gate and diffused layers.
A nonvolatile semiconductor memory device comprising:
- a trench formed in a semiconductor substrate;
- a floating gate formed in a bottom portion of the trench via a first gate insulating film;
- diffused layers, as sources or drain regions, which are formed in the semiconductor substrate on opposite sides of the floating gate;
- and
- first and second control gates which are positioned on the opposite diffused layers and which are formed on opposite side walls of the floating gate via an inter-gate insulating film and which drive the floating gate.
A nonvolatile semiconductor memory device comprising:
- a floating gate formed above a semiconductor substrate;
- first and second control gates which are formed on opposite sides of the floating gate and which are insulated from the floating gate and semiconductor substrate;
- a first capacitance between the semiconductor substrate and floating gate;
- a second capacitance between the first control gate and floating gate;
- a third capacitance between the second control gate and floating gate;
- a fourth capacitance between the first control gate and semiconductor substrate;
- and
- a fifth capacitance between the second control gate and semiconductor substrate.
A nonvolatile semiconductor memory device comprising:
- a cell transistor comprising a floating gate, source, and drain;
- and
- first and second control gates which are disposed on opposite sides of the floating gate of the cell transistor,
- wherein the floating gate is selected by the first and second control gates.
A nonvolatile semiconductor memory device comprising:
- cell transistors which comprise a floating gate, source, and drain and in which the adjacent sources and drains are connected in series;
- control gates disposed on opposite sides of the floating gate of each of the cell transistors;
- a first selection gate connected between one end of the cell transistors and bit line;
- and
- a second selection gate connected between the other end of the cell transistors and source line,
- wherein the control gates on the opposite sides of the floating gate select the floating gate.
Dependencies are inferred from the claim text.