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US 2004/0164334 A1Published application
Hybrid bulk/silicon-on-insulator multiprocessors
AssigneeFujitsu Limited
InventorsRobert P. Masleid, Gregory S. Scott
Life of this patent
Estimating the term…
Abstract
A multiprocessor integrated circuit is disclosed. A preferred embodiment of a multiprocessor chip has microprocessors formed on silicon-on-insulator regions and dynamic random access memory level-2 cache memories or level-3 cache memories formed on bulk regions of the chip. A preferred embodiment includes a redundant architecture having a signal bus for coupling the microprocessors to the level-2 or level-3 cache memories in which the signal bus includes a programmable selector circuit for bypassing defective microprocessors or defective level-2 or level-3 cache memories.
Claims26
An integrated circuit chip with redundant elements, comprising:
- a substrate die;
- a plurality of microprocessors disposed in said substrate die, each microprocessor having a data interface;
- a plurality of cache memories disposed in said substrate die, each cache memory having at least one memory interface for accessing the cache memory;
- and
- a signal bus disposed in said substrate die, said signal bus including a programmable selector circuit for selecting a subset of said plurality of microprocessors to be used for processing information and for selecting a subset of said plurality of cache memories, said selector circuit simultaneously linking the data interface of a first selected microprocessor to a memory interface of a first selected cache memory and linking the data interface of a second selected microprocessor to a memory interface of a second selected cache memory.
2 more elements
A multiprocessor chip, comprising:
- a silicon substrate die having at least one bulk region and at least one silicon-on-insulator region, the silicon-on-insulator region including a buried oxide layer residing a preselected distance between an outer surface layer of crystalline silicon;
- a plurality of microprocessors, each said microprocessor formed in said at least one silicon-on-insulator region, each microprocessor having a data interface;
- a plurality of dynamic random access memory (DRAM) cache memories formed in said at least one bulk region, each cache memory having a memory interface for accessing the cache memory;
- and
- a high bandwidth signal bus formed on said substrate having interconnect wires for linking the data interface of one microprocessor to a corresponding memory interface of one of the cache memories as a parallel processor.
2 more elements
A multiprocessor chip, comprising:
- a silicon substrate die having at least one bulk region and at least one silicon-on-insulator region, the silicon-on-insulator region including a buried oxide layer residing a preselected distance below an outer surface layer of crystalline silicon;
- a plurality of microprocessors, each said microprocessor formed in said at least one silicon-on-insulator region, each microprocessor having a data interface;
- a plurality of dynamic random access memory (DRAM) level-2 cache memories formed in said at least one bulk region, each level-2 cache memory having a memory interface for accessing the memory;
- and
- a high bandwidth signal bus formed on said substrate die having interconnect wires for linking the data interface of one microprocessor to a corresponding memory interface of one of the level-2 cache memories as a parallel processor, said signal bus including a programmable selector circuit for selecting a subset of said plurality of microprocessors and for selecting a subset of said cache memories to be used for parallel processing, said selector circuit simultaneously linking the data interface of a first selected microprocessor to the memory interface of a first selected cache memory and linking the data interface of a second selected microprocessor to the memory interface of a second selected cache memory, whereby a defective microprocessor or a defective cache memory may be bypassed.
2 more elements
A method of forming a multiprocessor chip on a silicon substrate, comprising the steps of:
- a) masking the substrate to form masked and unmasked regions;
- b) implanting said substrate with an oxygen ion implant having an energy and dose selected to form an implanted region underneath the surface of the substrate in the unmasked regions and bulk regions in the masked regions;
- c) annealing said substrate to form silicon-on-insulator in said implanted region;
- d) forming dense microprocessors in said implanted region via deep ultraviolet lithography;
- e) forming dynamic random access memory units in the bulk region of said substrate;
- and
- f) forming a signal bus for coupling said memory units to said microprocessors via a signal bus.
4 more elements
Dependencies are inferred from the claim text.