CMOS image sensor device and process of producing the same

A process for producing a CMOS image sensor device, comprising:

• providing a substrate;
• forming an isolation structure in the substrate to define an active region;
• forming a first well with first conductivity in the active region of the substrate;
• forming a second well with second conductivity under the isolation structure in the substrate;
• forming a gate dielectric layer over the substrate;
• forming a first conductive layer over the gate dielectric layer;
• patterning the first conductive layer and the gate dielectric layer to form an opening, wherein the opening exposes a predetermined surface of the substrate;
• performing a first ion implantation process to form a doped region in the substrate under the exposed surface;
• forming a second conductive layer over the substrate to fill the opening;
• patterning the second conductive layer and the first conductive layer to form a gate of the reset transistor and a third conductive layer, wherein the third conductive layer has a first end extending over the isolation structure and covering a peripheral portion of the isolation structure, and wherein the third conductive layer has a second end extending to the active region of the substrate to be as a gate of a source follower transistor;
• performing a thermal process to repair defects which occur on the sidewalls of the gate of the reset transistor and the third conductive layer, and drive the dopant of the doped region downward and then transversely diffuse them;
• performing a second ion implantation process to form a lightly doped region in the substrate outside sidewalls of the gate;
• forming a spacer respectively on the sidewalls of the gate of the reset transistor and the third conductive layer;
• performing a third ion implantation process to form a heavily doped region in the substrate where a drain region is later formed;
• and
• performing a thermal process to turn the lightly doped region and the doped region into a source region of the reset transistor, wherein the source region extends to the second well with second conductivity, and the heavily doped region and the lightly doped region form a drain region of the reset transistor.