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US 2004/0164326 A1Published application
Semiconductor memories
AssigneeHitachi, Ltd.
InventorsBryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
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Abstract
A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
Claims17
A semiconductor memory element comprised of:
- a plurality of word lines;
- a plurality of data lines;
- and
- memory cells at the intersections of the word lines and data lines,
- each memory cell being comprised of a storage transistor with a gate terminal electrically connected to a storage node and one of a source or drain region connected to a predetermined potential,
- a read transistor with a gate terminal electrically connected to a read word line and a source or drain region connected to the other one of said source or drain region of the storage transistor and the other one of the source or drain region of the read transistor connected to one of the data lines, and
- a semiconductor write device with a gate terminal electrically connected to a write word line and one of a source or drain region of the write transistor connected to another data line and the other one of the source or drain region of the write transistor connected to the storage node, wherein said semiconductor write device has a source region and drain region fabricated from metal or a semiconductor material connected by a channel which is formed by a semiconductor material with a thickness of no more than 5 nanometers on top of an insulating film, wherein said one side surface of said channel is substantially located on a same plane as said source region and drain region, and another side surface of said channel is located in different plane from said source region and drain region.
4 more elements
A semiconductor memory element, comprised of:
- a plurality of word lines;
- a plurality of data lines;
- and
- memory cells at the intersections of the word lines and data lines, each of said memory cells comprising a storage transistor with a gate terminal electrically connected to a storage node and one of a source or drain region is connected to a predetermined potential,
- a semiconductor write device activated by a write word line electrically connected to the storage node and one of a source or drain region of the semiconductor write device is connected to a one of the data lines and the other one of the source or drain region of the semiconductor write device is connected to the storage node, wherein said semiconductor device has a source region and drain region fabricated from a conductor connected by a channel which is formed by a semiconductor material of a thickness of no more than 5 nanometers on top of an insulating film, wherein said one side surface of said channel is substantially located on a same plane as said source region and drain region, and another side surface of said channel is located in different plane from said source region and drain region.
2 more elements
A semiconductor memory element, comprised of:
- a plurality of word lines;
- a plurality of data lines;
- and
- memory cells at the intersections of the word lines and data lines, each of said memory cells comprising a storage transistor with a gate terminal electrically connected to a storage node and one of a source or drain region is connected to a predetermined potential, and
- a semiconductor write device activated by a write word line electrically connected to the gate terminal of the write device and one of a source or drain region of the semiconductor write device connected to a one of the data lines and the other one of the source or drain region of the semiconductor write device connected to the storage node,
- wherein said semiconductor write device has a source region and drain region fabricated from metal or a semiconductor material connected by a channel which is formed by a semiconductor material with a thickness of no more than 5 nanometers on top of an insulating film, wherein said one side surface of said channel is substantially located on a same plane as said source region and drain region, and another side surface of said channel is located in different plane from said source region and drain region,
- wherein each of a pair of memory cells is connected to a separate data line and further wherein the source or drain regions of the semiconductor write devices of each of the pair of memory cells that are not connected to the storage nodes in the respective cells are electrically connected.
4 more elements
A semiconductor memory cell, comprising:
- a first switch element, and
- a first capacitor element, wherein a first terminal of the first capacitor element is electrically connected to a first terminal of the first switch element at a storage node, and a second terminal of the first capacitor element is connected to a reference potential, wherein said first switch element is adapted to transfer a charge to the storage node based on a voltage of an external data line, and the storage node is coupled to said external data line by capacitive coupling and
- further said external data line is adapted to obtain at least two voltage values Vd1 and Vd2, wherein said Vd1>Vd2 and, during a write operation to the memory cell, the charge stored at the storage node is Qs1 when a voltage of the external data lines is Vd1, and Qs2 when a voltage of the external data lines is Vd2, and wherein said Qs1 is smaller than said Qs2,
- wherein said switch element has a source region and drain region fabricated from metal or a semiconductor material connected by a channel which is formed by a semiconductor material with a thickness of no more than 5 nanometers on top of an insulating film, wherein said one side surface of said channel is substantially located on a same plane as said source region and drain region, and another side surface of said channel is located in different plane from said source region and drain region.
1 more element
A semiconductor memory element comprised of:
- a plurality of read and write word lines;
- a plurality of read and write data lines;
- and
- memory cells at the intersections of the word lines and data lines,
- each memory cell being comprised of a storage transistor with a gate terminal electrically connected to a storage node and one of a source or drain region connected to a predetermined potential,
- a read transistor with a gate terminal connected to a read word line and a source or drain region connected to the other one of said source or drain region of the storage transistor and the other one of the source or drain region of the read transistor connected to a read data line, and
- a semiconductor write device with a gate terminal electrically connected to a write word line and one of a source or drain region of the write device connected to a write data line and the other one of the source drain region of the write device connected to the storage node, wherein said semiconductor write device source region and drain region are fabricated from metal or a semiconductor material connected by a channel which is formed by a semiconductor material with a thickness of no more than 5 nanometers on top of an insulating film.
4 more elements
Dependencies are inferred from the claim text.