US 2004/0164304 A1Published application

Insulated gate planar integrated power device with co-integrated schottky diode and process

OwnerAngelo Magri, Ferruccio Frisinainventors

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Abstract

A process for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner does not requires a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages. A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the co-integrated device, is also disclosed.

Claims22

Dependent claims

An insulated gate planar power device with high packing density of the elementary cells that compose it, having a co-integrated Schottky diode electrically in parallel to the device formed in the area of each cell defined by an aperture through a polysilicon gate electrode, insulated from the underlying semiconductor by a dielectric gate layer, and through which such a co-integrated cell structure is constituted, each elementary cell comprising a body region formed in the semiconductor coupled to an invertible channel region under said insulated polysilicon gate electrode for establishing conditions of inversion of said channel region, a source region formed in the area of said cell aperture within said body region, a drain region in said semiconductor coupled to said invertible channel region, a trench formed in said semiconductor in a portion of the area of said cell aperture having a depth extending from the surface of the semiconductor through said source region and said body region, a source metal layer contacting over the sides of said trench said source region and said body region for establishing a source contact and said drain region at the bottom of said trench to establish a Schottky diode contact, electrically in parallel to the elementary cell of the integrated insulated gate device, characterized in that

said trench is self aligned to dielectric spacers formed on the definition edges surfaces of said aperture in a portion of the area of the aperture that includes a central “window” defined in a shade pattern of slanted body dopants implant, for a greater depth than the bottom of said source region and sufficient to expose at the bottom of the trench said drain region in the semiconductor bordered by said body region at least along two opposite sides;
said contact metal fills said central trench establishing an electric contact with said source region and with said body region on at least a portion of the surface of the lateral sides of said trench and said Schottky contact on at least a portion of the bottom surface of said trench.

A process for fabricating an insulated gate integrated power device comprising the steps of:

a) constituting a drain semi conducting substrate doped with a dopant of a first type of conductivity and forming an edge structure of the insulated gate integrated power device,
b) forming an insulated gate electrode by growing or depositing a dielectric film of gate oxide on the surface of said drain semiconducting substrate and depositing thereon a conductive layer of polysilicon,
c) covering said conductive polysilicon layer with an insulating layer or multilayer of dielectric material deposited thereon,
d) depositing a layer of photo resist on said deposited insulating layer,
e) defining said gate electrode by masking and anisotropic selective etching of said deposited insulating layer and of said polysilicon layer forming apertures through the area of which the integrated structure and the relative source contact of each elementary cell constituting said power device will be formed,
and characterized in that the successive sequence comprises the steps of
f) performing a first ion implantation of a dopant appropriate to constitute a body region of opposite type of conductivity of said drain semiconducting substrate with certain tilt and twist angles such to determine a shade zone inside said aperture in function of the total height of the definition edge of the stack composed of said polysilicon layer, said insulating layer and said layer of photo resist, and of the width of the aperture, with an implant dose and energy appropriate to obtain a certain concentration and channel length;
g) performing at least a second ion implantation at the same conditions of said first implantation but with different tilt and twist angles to define a central window in the shade pattern on the implanted cell area;
h) removing of said layer of photo resist;
i) activating the implanted dopants by heat treatment;
j) performing a source ion implantation on the whole area of said aperture of a dopant of the same type of conductivity of the drain substrate and opposite to that of the dopant of said body implantations with dose and energy of implant appropriate to constitute a source region surrounded by said body region;
k) activating of the implanted source dopant by heat treatment;
l) depositing a sacrificial layer of a dielectric material under conditions of substantial uniformity of thickness of deposition over the steps of the definition borders of said apertures;
m) anisotropic etching of the sacrificial layer for leaving a dielectric spacer on the definition edge surfaces of said apertures;
n) anisotropic etching of the semiconductor for a depth deeper than the depth of said source region but shallower than the depth of said body region, exposing within the area of each cell surfaces of said source region, of said body region and, at the bottom of the trench, a zone of said drain substrate surrounded laterally by said body region;
o) opening of contacts on said gate electrode through a dedicated photo resist mask;
p) removing the photo resist mask and depositing one or more conductive metal layers for establishing inside said trench an electric contact with both the source region and the body region and determining a good barrier height of the Schottky contact established with the drain substrate on at least a portion of the bottom surface of said trench.

14 more elements

A process for fabricating an insulated gate integrated power device comprising the steps of:

a) constituting a drain semi conducting substrate doped with a dopant of a first type of conductivity and forming an edge structure of the insulated gate integrated power device,
b) forming an insulated gate electrode by growing or depositing a dielectric film of gate oxide on the surface of said drain semi conducting substrate and depositing thereon a conductive layer of polysilicon,
c) covering said conductive polysilicon layer with an insulating layer or multilayer of dielectric material deposited thereon,
d) depositing a layer of photo resist on said deposited insulating layer,
e) defining said gate electrode by masking and anisotropic selective etching of said deposited insulating layer and of said polysilicon layer forming apertures through the area of which the integrated structure and the relative source contact of each elementary cell constituting said power device will be formed,
and characterized in that the successive sequence comprises the steps of
f) performing a first ion implantation of a dopant appropriate to constitute a deep body region of opposite type of conductivity of said drain semi conducting substrate with certain tilt and twist angles such to determine a shade zone inside said aperture in function of the total height of the definition edge of the stack composed of said polysilicon layer, said insulating layer and said layer of photo resist, and of the width of the aperture, with an implant dose and energy appropriate to obtain a certain concentration and depth of implant;
g) performing at least a second ion implantation at the same conditions of said first implantation but with different tilt and twist angles to define a central window in the shade pattern on the implanted cell area;
h) removing said layer of photo resist;
i) performing at least a third ion implantation of a dopant appropriate to constitute a body region of opposite type of conductivity of said drain semi conducting substrate with certain tilt and twist angles such to determine a shade zone inside said aperture in function of the total height of the definition edge of the stack composed of said polysilicon layer and said insulating layer, and of the width of the aperture, with an implant dose and energy appropriate to obtain a certain concentration and channel length;
j) performing at least a fourth ion implantation at the same conditions of said third implantation but with different tilt and twist angles to define a central window in the shade pattern on the implanted cell area
k) activating the implanted body and deep body dopants by heat treatment;
l) performing a source ion implantation on the whole area of said aperture of a dopant of the same type of conductivity of the drain substrate and opposite to that of the dopants of said body and deep body implantations, with dose and energy of implant appropriate to constitute a source region surrounded by said body region;
m) activating the implanted source dopant by heat treatment;
n) depositing a sacrificial layer of a dielectric material under conditions of substantial uniformity of thickness of deposition over the steps of the definition borders of said apertures;
o) anisotropic etching of the sacrificial layer for leaving a dielectric spacer on the definition edge surfaces of said apertures;
p) anisotropic etching of the semiconductor for a depth deeper than the depth of said source region but shallower than the depth of said body region, exposing within the area of each cell surfaces of said source region, of said body region, and, at the bottom of the trench, said deep body region and a zone of said drain substrate surrounded laterally by said deep body region;
q) opening of contacts on said gate electrode through a dedicated photo resist mask;
r) removing the photo resist mask and depositing one or more conductive metal layers for establishing inside said trench an electric contact with both the source region and the body region and determining a good barrier height of the Schottky contact established with the drain substrate on at least a portion of the bottom surface of said trench.

16 more elements

An insulated gate planar power device with a Schottky diode in parallel thereto, said Shottky diode being realized by contacting with a metal layer a semiconductor substrate of a first type of conductivity and the contact zone being laterally surrounded by one or more diffused regions of opposite type of conductivity formed in said substrate for shielding the electric field under conditions of reverse bias of the diode, characterized in that it comprises, in said semiconducting substrate, a buried region doped with a dopant of opposite type of conductivity to that of said semiconductor substrate, geometrically located under said Schottky contact zone and at a greater depth than the depth of said diffused regions.

Dependencies are inferred from the claim text.