Full wafer contacter and applications thereof

An apparatus adapted for electrical testing, comprising:

• a substrate including a plurality of non-singulated integrated circuits, the plurality of integrated circuits each having at least one terminal disposed on at least a first major surface of the substrate, the terminals adapted for electrical connection to an external device;
• and
• a full wafer contacter attached to the first major surface of the substrate;
• wherein the full wafer contacter comprises:
• an electrically insulating body having at least two major surfaces;
• a first plurality of electrical contacts disposed on a first major surface of the body;
• a second plurality of electrical contacts disposed on a second major surface of the body;
• a plurality of electrical vias disposed in the body, between the first major surface and the second major surface so as to provide electrically conductive paths between at least a portion of the first plurality electrical contacts and a corresponding portion of the second plurality of electrical contacts;
• and
• an evacuation pathway disposed in the electrically insulating body, the evacuation pathway adapted to provide access to one or more gases;
• and
• an evacuation pathway sealing means adapted to maintain a pressure established between the full wafer contacter and the substrate.

A method of electrically accessing a plurality of integrated circuits, each integrated circuit having a plurality of terminals, the method comprising:

• providing a wafer having a first and a second major surface, the plurality of integrated circuits disposed on a first major surface thereof, each of the plurality of integrated circuits having a plurality of terminals, and the plurality of integrated circuits disposed over at least a portion of the first major surface;
• providing a full wafer contacter having a first major surface and a second major surface, a first plurality of contact terminals disposed on the first major surface of the full wafer contacter in a pattern that corresponds to the terminal layout of the plurality of integrated circuits;
• and
• removably attaching the full wafer contacter to the wafer such that the first major surface of the wafer and the first major surface of the full wafer contacter are facing each other, and such that at least a portion of the terminals of the integrated circuits are in electrical contact with the first plurality of contact terminals;
• wherein each of the first plurality of contact terminals is electrically coupled to a corresponding one of a second plurality of contact terminals disposed on the second major surface of the full wafer contacter.