Memory devices and electronic systems comprising integrated bipolar and FET devices

A memory cell construction, comprising:

• an electrically insulative material;
• a crystalline layer comprising silicon and germanium over the electrically insulative material;
• a field effect transistor comprising a gate over the crystalline layer and an active region extending into the crystalline layer, the active region of the field effect transistor including a pair of source/drain regions;
• and
• a bipolar transistor having a collector region, emitter region and base region;
• the base region electrically connecting with one of the source/drain regions.

A memory cell construction, comprising:

• an electrically insulative material;
• a first crystalline Si/Ge layer over the electrically insulative material;
• the first crystalline Si/Ge layer having a relaxed crystalline lattice;
• a second crystalline Si/Ge layer over the first crystalline Si/Ge layer;
• the second crystalline Si/Ge layer having a strained crystalline lattice;
• a field effect transistor comprising a gate over the second crystalline Si/Ge layer and an active region extending into the first and second crystalline Si/Ge layers, the active region of the field effect transistor including a pair of source/drain regions;
• the active region within the first Si/Ge layer being within a single crystal of the first Si/Ge layer;
• and
• a bipolar transistor having a collector region, emitter region and base region;
• the base region electrically connecting with one of the source/drain regions;
• an entirety of the collector region and emitter region being above the field effect transistor gate.

An electronic system, the electronic system comprising a memory device, the memory device including:

• an array of memory cells, at least some of the memory cells including a field effect transistor and a bipolar transistor;
• the field effect transistors having transistor gates and active regions comprising source/drain regions;
• the active regions extending into a crystalline Si/Ge layer;
• the bipolar transistors having collector regions, emitter regions and base regions;
• the collector regions and emitter regions being above the transistor gates;
• the base regions electrically connecting with source/drain regions of the field effect transistors;
• addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells;
• and
• a read circuit coupled to the memory cell array for reading data from memory cells in the array of memory cells.