Methods of fabricating multiple sets of field effect transistors

A method of fabricating multiple sets of field effect transistors, comprising:

• forming an etch stop layer over an insulative capping layer over a conductive gate layer over a substrate;
• patterning and etching the etch stop layer, the insulative capping layer, and the conductive gate layer to form a first set of conductive gate constructions over the substrate;
• forming and anisotropically etching an insulative spacer forming layer over the first set of conductive gate constructions effective to form insulative spacers, the etch stop layer restricting etching of the insulative capping layer during the anisotropically etching;
• after forming the insulative spacers, forming and planarizing a dielectric material over the first set of gate constructions;
• and
• after forming and planarizing the dielectric material, patterning and etching the insulative capping layer and the conductive gate layer to form a second set of conductive gate constructions over the substrate.

A method of fabricating multiple sets of field effect transistors, comprising:

• forming an etch stop layer over an insulative capping layer over a conductive gate layer over a substrate, the etch stop layer being formed to a first thickness;
• patterning and etching the etch stop layer, the insulative capping layer, and the conductive gate layer to form a first set of conductive gate constructions over the substrate;
• forming and anisotropically etching an insulative spacer forming layer over the first set of conductive gate constructions effective to form insulative spacers, the etch stop layer restricting etching of the insulative capping layer during the anisotropically etching;
• after forming the insulative spacers, forming and planarizing a dielectric material over the first set of gate constructions, and effective to remove all remaining of the etch stop layer from the substrate during said planarizing;
• after forming and planarizing the dielectric material, forming a mass of material over the substrate to a second thickness which is within ten percent of the first thickness;
• and
• after forming and planarizing the dielectric material, patterning and etching the mass of material, the insulative capping layer and the conductive gate layer to form a second set of conductive gate constructions over the substrate.