Mask-programmable logic device with building block architecture
AssigneeAltera Corporation
InventorsKim Pin Tan, Boon Jin Ang, Bee Yee Ng
Life of this patent
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Abstract
A mask-programmable logic device includes logical building blocks that can be connected together to form various logical units for programmable logic. Functionality of a comparable conventional programmable logic device can be provided with fewer gates in this way than by providing all of the gates normally present on that comparable conventional programmable logic device, resulting in fewer unused gates in the devices once mask-programmed.
Claims39
A mask-programmable logic device comprising:
- an array of programmable logic sub-units, said logic sub-units comprising:
- a plurality of intelligent macrocells and a plurality of gate arrays, each of said intelligent macrocells and said gate arrays having contacts for connection to an interconnect structure for connecting said logic sub-units into a plurality of logic units and configuring said plurality of logic units to perform one or more logic functions.
A mask-programmed logic device comprising:
- an array of programmable logic sub-units, said logic sub-units comprising:
- a plurality of intelligent macrocells and a plurality of gate arrays;
- and
- at least one programming metallization layer that:
- (a) programs said programmable logic subunits, and (b) provides interconnections between and among said programmed logic sub-units.
A method of programming a mask-programmable logic device, said method comprising:
- providing a mask-programmable base device including an array of programmable logic sub-units, said logic sub-units comprising a plurality of intelligent macrocells and a plurality of gate arrays, each of said intelligent macrocells and said gate arrays;
- and
- applying at least one programming metallization layer that (a) programs said programmable logic sub-units, and (b) provides interconnections between and among said programmed logic sub-units.
A logic device comprising:
- an array of programmable logic sub-units, said logic sub-units comprising:
- a plurality of intelligent macrocells and a plurality of gate arrays, each of said intelligent macrocells and said gate arrays having contacts for connection to an interconnect structure for connecting said logic sub-units into a plurality of logic units and configuring said plurality of logic units to perform one or more logic functions.
Dependencies are inferred from the claim text.