Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages

A computer program product that is configured to generate an integrated circuit netlist, comprising a computer-readable storage medium having computer-readable program code embodied in said medium, said computer-readable program code comprising:

• computer-readable program code that is configured to generate a first schematic of an integrated circuit having a plurality of cells therein;
• computer-readable program code that is configured to generate a second schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximate parasitic resistances and parasitic capacitances of the post-layout interconnects;
• and
• computer-readable program code that is configured to combine the first and second schematics at corresponding first and second ports within the first and second schematics, respectively.

A method of generating an integrated circuit netlist, comprising the steps of:

• generating a first schematic of an integrated circuit having a plurality of cells therein;
• generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects;
• and
• combining the first and second schematics at corresponding first and second ports within the first and second schematics, respectively.

An integrated circuit netlist generation apparatus, comprising:

• means for generating a first schematic of an integrated circuit having a plurality of cells therein;
• means for generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects;
• and
• means for combining the first and second schematics at corresponding first and second ports within the first and second schematics, respectively.

A selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the device comprising:

• a selective netlist processor for generating a selective netlist of a schematic circuit including cells, a simulation schematic circuit obtained by combining the schematic circuit and an interconnection schematic circuit, and cells performing specific operations of the simulation schematic circuit, in response to input information including information on circuit devices included in the respective cells, information on connections between the circuit devices, and schematic layout information of the cells, a netlist of parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections interconnecting the cells, and selection information for selecting cells performing specific operations among the cells;
• a layout generator for generating a layout of the semiconductor integrated circuit in response to the information on the schematic circuit provided from the selective netlist processor;
• and
• a parasitic RC extractor for extracting a netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections, generated from the layout generator and providing the extracted netlist to the selective netlist processor.

A selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the device comprising:

• a selective netlist processor for generating a selective netlist of a schematic circuit including cells, a first simulation schematic circuit obtained by combining the schematic circuit and an interconnection schematic circuit, a second simulation schematic circuit obtained by combining the schematic circuit and a schematic circuit corresponding to a netlist of parasitic resistance and parasitic capacitance, and cells performing specific operations of the simulation schematic circuit, in response to input information including information on circuit devices included in the respective cells, information on connections between the circuit devices, and schematic layout information of the cells, information the interconnections interconnecting the cells, and selection information for selecting cells performing specific operations among the cells;
• an interconnection generator for generating the interconnections in response to positional information of the cells included in the schematic circuit provided from the selective netlist processor and providing the generated information on the interconnections;
• a layout generator for generating a layout of the semiconductor integrated circuit in response to the information on the schematic circuit provided from the selective netlist processor;
• and
• a parasitic RC extractor for extracting a netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections, generated from the layout generator, and providing the extracted netlist to the selective netlist processor.

A method for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the method comprising:

• (a) generating a schematic circuit in response to input information including information on circuit devices included in respective cells, information on connections between the circuit devices, and schematic layout information of the cells;
• (b) generating interconnections interconnecting the cells in response to positional information of the cells included in the generated schematic circuit;
• (c) generating an interconnection schematic circuit including parasitic resistance and parasitic capacitance, which are parasitic on the generated interconnections;
• (d) combining first ports included in the cells of the generated schematic circuit with second ports of the interconnection schematic circuit, corresponding to the first ports, to generate a simulation schematic circuit;
• and
• (e) selecting specific cells in response to selection information for selecting cells performing specific operations of the simulation schematic circuit and generating a selective netlist of the selected cells.

A method for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the method comprising:

• (a) generating a schematic circuit in response to input information including information on circuit devices included in respective cells, information on connections between the circuit devices, and schematic layout information of the cells;
• (b) generating a layout of the semiconductor integrated circuit in response to the information on the generated schematic circuit;
• (c) extracting a netlist including parasitic resistance and parasitic capacitance, which are parasitic on the generated layout of interconnections;
• (d) generating an interconnection schematic circuit including the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections, in response to the extracted netlist;
• (e) combining first ports included in cells of the generated schematic circuit with second ports of the interconnection schematic circuit, corresponding to the first ports, to generate a simulation schematic circuit;
• and
• (f) selecting specific cells of the simulation schematic circuit in response to selection information for selecting cells performing specific operations of the generated simulation schematic circuit.

A method for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the method comprising:

• (a) generating a schematic circuit in response to input information including information on circuit devices included in respective cells, information on connections between the circuit devices, and schematic layout information of the cells;
• (b) generating interconnections interconnecting cells in response to positional information of the cells included in the generated schematic circuit;
• (c) generating a first interconnection schematic circuit including parasitic resistance and parasitic capacitance, which are parasitic on the generated interconnections;
• (d) combining first ports included in cells of the generated schematic circuit with second ports of the interconnection schematic circuit, corresponding to the first ports, to generate a first simulation schematic circuit;
• (e) generating a layout of the semiconductor integrated circuit in response to the information on the generated schematic circuit;
• (f) extracting a netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the generated layout of the interconnections;
• (g) generating a second interconnection schematic circuit including the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections, in response to the extracted netlist;
• (h) combining first ports included in the cells of the generated schematic circuit and second ports of the second interconnection schematic circuit, corresponding to the first ports, to generate a second simulation schematic circuit and replace the stored first simulation schematic circuit by the second simulation schematic circuit;
• and
• (i) selecting specific cells of the second simulation schematic circuit in response to selection information for selecting cells performing specific operations of the replaced second simulation schematic circuit and generating a selective netlist of the selected cells.