Method for faster timing closure and better quality of results in IC physical design
AssigneeVIA Technologies, Inc.
InventorsXin Chang, Penny Wang, Shuming Chuang
Life of this patent
Estimating the term…
Abstract
A selective IPO procedure based on the concept of a “timing violation potential” prioritizes the components and nets in a critical path. User input criteria is used to select the components or nets (or both) which have the larger “timing violation potential;” only those components and nets are then operated on. After a selective IPO step, the total number of critical paths is reduced, as well as the worst negative slacks (WNS) of the critical path compared to the traditional IPO method.
Claims7
A method of resolving timing violations in a network of components and interconnects for a physical design of an integrated circuit, the method comprising:
- performing a timing analysis on the network, one or more components or interconnects of the network each having a particular amount of timing violation potential;
- and
- performing a selective in-place optimization by identifying components or interconnects of the network that have the highest amount of timing violation potential and executing an in place optimization according to the identified components or interconnects.
A computer program embodied on a computer readable medium for resolving timing violations in a network of components and interconnects for a physical design of an integrated circuit, the computer program comprising:
- code for performing a timing analysis on the network, one or more components or interconnects of the network each having a particular amount of timing violation potential;
- and
- code for performing a selective in-place optimization by identifying components or interconnects of the network that have the highest amount of timing violation potential and executing an in place optimization according to the identified components or interconnects.
A system for resolving timing violations in a network of components and interconnects for a physical design of an integrated circuit, the system comprising:
- a processor for performing a timing analysis on the network, one or more components or interconnects of the network each having a particular amount of timing violation potential;
- and
- means for performing a selective in-place optimization by identifying components or interconnects of the network that have the highest amount of timing violation potential and executing an in place optimization according to the identified components or interconnects.
Dependencies are inferred from the claim text.