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US 2004/0111684 A1Published application
Design method of logic circuit
AssigneeKabushiki Kaisha Toshiba
InventorAtsushi Masuda
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AssigneeKabushiki Kaisha Toshiba
InventorAtsushi Masuda
Estimating the term…
An algorithm of a logic circuit is converted from an operation description having operators into a data flow graph having operation nodes executing the operators arranged in order of the executing. Execution steps are allocated in the data flow graph, and registers storing output data from the operation nodes are inserted after execution of the execution steps. A data path of the logic circuit having operation units which served as the operation nodes and storage elements which served as the registers, and control information on the data path are produced. An operator/operation unit database configured to retrieve the operation units executing the operators from the operators and configured to retrieve the operators outputting data stored in the registers which served as the storage elements from the execution steps and the storage elements are produced.
A computer-implemented design method of a logic circuit comprising:
A computer program product to be executed by a computer for designing a logic circuit, the computer program product comprising:
An apparatus for designing a logic circuit comprising:
Dependencies are inferred from the claim text.
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Computer-aided design [CAD]: circuit design
Computing and data processing
Term end not estimated
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. P2002-354208, filed on Dec. 5, 2002; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a high level synthesizing technique for automatically generating a register transfer level (abbreviated as “RTL”) description and, more particularly, to a design method of a logic circuit for converting an operation description into an RTL description.
FIG. 1 is a diagram illustrating the configuration of an apparatus for designing a logic circuit in embodiments according to the present invention;
FIG. 2 is a diagram illustrating the flow of data in the apparatus for designing a logic circuit in the embodiments according to the present invention;
FIG. 3 is a flowchart illustrating a design method of a logic circuit in the embodiments according to the present invention;
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
[Apparatus for Designing Logic Circuit]
As illustrated in FIG. 1, a apparatus 1 for designing a logic circuit in embodiments according to the present invention comprises: a syntactic analyzing unit 2, a scheduling unit 3, an optimizing unit 4, a hardware allocating unit 5, an RTL description producing unit 6, a node/operator correspondence information analyzing unit 7, a node/operation unit correspondence information analyzing unit 8, an operator/operation unit correspondence information analyzing unit 9, an operation description simulating unit 10, an RTL description simulating unit 11, a simulation result comparing unit 12 and an input/output unit 16. The simulation result comparing unit 12 includes an operator retriever 13, a storage data determiner 14 and an operation unit retriever 15.