Vector logic techniques for multilevel minimization
AssigneeJonathan Westphal
InventorJonathan Westphal
Life of this patent
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Abstract
Very complex (multilevel) logical expressions are represented in a vector format. The logic is simplified by identifying opposing couples (a literal and its negation) and replacing symmetrical logic expressions attached to the opposing couples with a single version. Significant simplification of the logic can thus be achieved that is suitable for applications in CAD/CAM and in design and manufacture of integrated circuits. The simplification results in increased reliability, lower cost and faster circuits.
Claims12
Apparatus for the design of logic circuits, comprising:
- a. a computer, and
- b. software stored on the computer for
- b1. representing multilevel logic schema in vector form;
- and for
- b2. simplifying multilevel logic schema into a simplified form by exploiting symmetries in the logical schema.
A method of reducing multilevel logic to simpler form comprising the steps of:
- a. representing the logic in vector form;
- and
- b. removing redundancy by eliminating opposing couples.
A system for the design or manufacturing of logical circuits, comprising:
- a. a plurality of computers connected to a network;
- b. at least one of said computers having software stored thereof for
- b1. representing multilevel logic schema in vector form;
- and for
- b2. simplifying multilevel logic schema into a simplified form by exploiting symmetries in a logical schema.
A computer program product, comprising:
- a. a computer readable storage medium;
- and
- b. at least one computer program stored on said storage medium, said at least one computer program comprising instructions for:
- b1. representing multilevel logic schema in vector form;
- and for
- b2. simplifying multilevel logic schema into a simplified form by exploiting symmetries in the logical schema.
A computer program product, comprising:
- a. a computer readable storage medium;
- and
- b. at least one computer program stored on said storage medium, said at least one computer program comprising instructions for:
- b1. representing the logic in vector form;
- and
- b2. removing redundancy by eliminating opposing couples.
A method of manufacturing integrated circuits comprising the steps of:
- a. representing at least a portion of the logic circuits to be incorporated into the integrated circuit in vector form;
- and
- b. simplifying the logic by removing redundancy by eliminating opposing couples.
A method of manufacturing integrated circuits comprising the steps of:
- a. representing at least a portion of the logic circuits to be incorporated into the integrated circuit in vector form;
- and
- b. simplifying the logic by removing redundancy by exploiting symmetries in the logical schema.
A method of reducing multilevel logic to simpler form comprising the steps of:
- a. representing the logic in vector form;
- b. identifying opposing couples having at least symmetrical logic comprising some similarities in logical expression that connects to them;
- c. removing redundancy by eliminating an opposing couples and sliding the symmetrical logic attached to opposing couples onto a point common to the opposing couples.
Dependencies are inferred from the claim text.