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US 2004/0111682 A1Published application
Integrated circuit design layout compaction method
AssigneeNeolinear, Inc.
InventorsPrakash Gopalakrishnan, Rob A. Rutenbar, Elias Fallon
Life of this patent
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Abstract
A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.
Claims35
A circuit design layout compaction method comprising:
- (a) defining a conformal outline having a pair of spaced parallel sides;
- (b) defining in the conformal outline a first member device and a second member device;
- (c) associating with each member device a spacing constraint that sets a minimum distance the member device can be spaced from the other member device and each side of the conformal outline;
- (d) decreasing a spacing between the first and second member devices such that no further decrease in spacing therebetween can occur without violating a spacing constraint;
- and
- (e) decreasing the spacing between the sides of the conformal outline such that no further decrease in spacing between the sides can occur without at least one of the sides violating a spacing constraint.
3 more elements
A circuit design layout compaction method comprising:
- (a) defining a plurality of adjacent conformal outlines and a plurality of member devices positioned in at least one of the conformal outlines, with each conformal outline having a pair of spaced parallel sides, with each pair of adjacent conformal outlines having sides that overlap;
- (b) associating with each member device a spacing constraint that sets a minimum distance the member device can be spaced from another member device and a portion of any side that does not overlap another side;
- (c) decreasing a spacing between at least one pair of member devices such that no further decrease in spacing between the one pair of member devices can occur without violating a spacing constraint;
- and
- (d) subject to the sides of each pair of adjacent conformal outlines remaining overlapping, decreasing the spacing between the sides of each conformal outline such that no further decrease in spacing between the sides of each conformal outline can occur without at least one of the sides violating a spacing constraint.
2 more elements
A circuit design layout compaction method comprising:
- (a) defining a conformal outline having a pair of spaced parallel sides;
- (b) defining in the conformal outline a first member device and a second member device, with each member device having associated therewith a spacing constraint that sets a minimum distance the member device can be spaced from the other member device and from each side of the conformal outline, with the first and second member devices defined in the conformal outline with a violation of one of the spacing constraints thereof;
- and
- (c) increasing the spacing between the first and second member devices whereupon the violation of the one spacing constraint is overcome.
1 more element
A circuit design layout compaction method comprising:
- (a) defining a plurality of adjacent conformal outlines, with each conformal outline having a pair of spaced parallel sides, with each pair of adjacent conformal outlines having sides that overlap;
- (b) defining a plurality of member devices in at least one of the conformal outlines, with each member device having a spacing constraint associated therewith that sets a minimum distance the member device can be spaced from another member device and a portion of any side that does not overlap another side, with at least two member devices defined in the conformal outlines with a violation of one of the spacing constraints thereof;
- and
- (c) increasing a spacing between the two member devices whereupon the violation of the one spacing constraint is overcome.
1 more element
A circuit design layout compaction method comprising:
- (a) defining a first layout of a plurality of member devices having a conformal outline therearound, the conformal outline having a pair of spaced parallel sides;
- (b) associating with each member device a spacing constraint that sets a minimum distance the member device can be spaced from at least one of another member device and from each side of the conformal outline;
- (c) where the first layout has a violation of at least one spacing constraint, defining therefrom a second layout of the member devices having an increased spacing between each pair of member devices having a violation of at least one of the spacing constraints thereof in the first layout whereupon, in the second layout, the at least one spacing constraint violation is overcome;
- and
- (d) where one of the first and second layouts has no violation of at least one spacing constraint, defining therefrom a third layout of the member devices having a decreased spacing between at least one pair of member devices whereupon no further decreases in spacing between each pair of member devices can occur without violating at least one spacing constraint.
2 more elements
A circuit design layout compaction method comprising:
- (a) defining a plurality of adjacent conformal outlines and a first layout of a plurality of member devices in at least one of the conformal outlines, with each conformal outline having a pair of spaced parallel sides, with each pair of adjacent conformal outlines having sides that overlap;
- (b) associating with each member device a spacing constraint that sets a minimum distance the member device can be spaced from at least one of another member device and from each nonoverlapping portion of each side of each conformal outline;
- (c) where the first layout has a violation of at least one spacing constraint, defining therefrom a second layout of the member devices having an increased spacing between each pair of member devices having a violation of at least one of the spacing constraints thereof in the first layout whereupon, in the second layout, the at least one spacing constraint violation is overcome;
- and
- (d) where one of the first and second layouts has no violation of at least one spacing constraint, defining therefrom a third layout of the member devices having a decreased spacing between at least one pair of member devices whereupon no further decreases in spacing between each pair of member devices can occur without violating at least one spacing constraint.
2 more elements
Dependencies are inferred from the claim text.