CRC verification apparatus with constant delay and method thereof

A CRC verification apparatus having constant delay, comprising:

• a buffer which stores an input data frame and control information on a data frame;
• a CRC generation unit which performs CRC verification of the data frame;
• an input control unit which receives an input control signal, generates a CRC enable signal, sends the CRC enable signal to the CRC generation unit, generates information on a write address which increases sequentially irrespective of the input of the data frame, sends the write address information to the buffer, and with storing an address in which the start part of the data frame is stored, if input of the data frame finishes, receives the CRC verification result from the CRC generation unit and stores the CRC verification result in the address in which the start part of the data frame is stored, and provides a read address synchronization signal that makes a read address follows with a predetermined offset after the write address;
• and
• an output control unit which receives the read address synchronization signal, generates the read address which increases sequentially, sends the read address information to the buffer, reads data stored in the buffer, and outputs a different output control signal together with the data according to the CRC result.

A CRC verification method having constant delay, comprising:

• storing an input data frame and recording the start address in which the data frame is stored;
• performing CRC verification of the data frame;
• receiving an input control signal, generating a CRC enable signal, generating write address which increases sequentially irrespective of the input of the data frame, and with storing an address in which the start part of the data frame is stored, if input of the data frame finishes, receiving the CRC verification result from the CRC generation unit and storing the CRC verification result in the address in which the start part of the data frame is stored, and providing a read address synchronization signal that makes the read address follow with a predetermined offset after the write address;
• and
• receiving the read address synchronization signal, generating information on a read address which increases sequentially, reading the stored data frame according to this read address information, and according to the CRC result, outputting a different output control signal together with the output data.