Memory device with debug mode

A method of debugging an electronic device, comprising;

• providing a memory device with a debug mode to integrate into the electronic device, wherein the memory device has a memory unit accessing corresponding data according to an address signal and a command signal, three buffers coupled to the memory device and a debug mode controller controlling the three buffers to store the address signal, the command signal and the corresponding data;
• detecting whether the address signal, the command signal and the corresponding data change;
• enabling the three buffers to store the address signal, the command signal and the corresponding data when the address signal, the command signal and the corresponding data change;
• reading out the address signal, the command signal and the corresponding data;
• and
• executing a debug analysis according to the address signal, the command signal, and the corresponding data.

An electronic device, comprising:

• a main body having a plurality of required programs and a microprocessor executing the required programs, wherein the control unit outputs an enable signal to enter a debug mode;
• and
• a memory device with debug mode disposed in the electronic device, comprising:
• a memory unit for accessing corresponding data according to an address signal and a command signal when the microprocessor executes the required programs;
• three buffers coupled to the memory unit;
• and
• a debug mode controller for detecting whether the address, the command signal and the corresponding data change and enabling the three buffers to store the address signal, the command signal and the corresponding data according to the enable signal;
• wherein the microprocessor executes a debug analysis according to the address signal, the command signal and the corresponding data stored in the three buffers.