System and method for managing a cache memory
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.
Claims49
A method of searching a string of data for a match with a test data string, the method comprising:
- receiving an instruction to perform a search operation, the instruction comprising a starting address for the search operation;
- routing the instruction to a data string manipulation circuit;
- routing the starting address for the search operation from the data string manipulation circuit to a cache memory array;
- comparing a test data string with data stored in the cache memory array;
- and
- routing an address of cached data matching the test data string to the data string manipulation circuit.
A method of performing a cache search operation within a digital processing system, the method comprising:
- receiving an instruction to perform a search operation, the instruction comprising a starting address and a test data string;
- routing the instruction to a data string manipulation circuit;
- routing the starting address for the search operation from the data string manipulation circuit to a cache memory;
- searching a cache line in the cache memory for data that matches the test data string, wherein said cache line comprises more bytes than the test data string;
- and
- routing an address of cached data matching the test data string to the data string manipulation circuit.
A data cache circuit for searching for a data value in a cache memory, the data cache circuit comprising:
- a cache data memory comprising a cache line comprising a plurality of bytes of data;
- a data source configured to hold a data value, the data value comprising less bytes than the cache line;
- an instruction processor configured to search the entire cache line for data matching the data value, the instruction processor comprising:
- a first set of inputs coupled to the cache data memory, each of the first set of inputs configured to receive at least one of said plurality of bytes of data of the cache line;
- a second set of inputs coupled to the data source and configured to receive at least a portion of the data value from the data source;
- and
- a plurality of outputs;
- and
- a decoder coupled to the outputs of the instruction processor and configured to identify a portion of the cache line that matches at least a portion of the data value.
A processor comprising:
- a data memory comprising a plurality of cache lines, each cache line comprising a plurality of bytes of data;
- an instruction processing circuit configured to receive a test data string and an instruction to perform a search operation, the instruction processing circuit comprising a plurality of inputs coupled to the data memory such that each input is coupled to receive one of the plurality of bytes of data of the cache line, the instruction processing circuit further comprising a plurality of outputs;
- and
- a decoder coupled to the plurality of outputs of the instruction processing circuit and configured to identify a portion of the cache line having data that matches at least a portion of the test data string.
A cache memory circuit comprising:
- a data source means for holding a data value;
- a cache data memory means for holding at least one cache line comprising a plurality of bytes of data;
- and
- a means for searching the cache line, wherein said means for searching is coupled to said cache memory means and said data source means such that the cache line may be searched in one clock cycle for data that matches the data value.
Dependencies are inferred from the claim text.