Multithreading recycle and dispatch mechanism

An in-order multithreading processor having two or more threads, comprising:

• a plurality of instruction fetch address registers, at least one of the instruction fetch address registers being assigned to each of the two of more threads;
• an instruction cache coupled to the plurality of instruction fetch address registers;
• a plurality of instruction buffers, at least one of the instruction buffers being assigned to each thread, the plurality of instruction buffers being coupled to the instruction cache for receiving one or more instructions from the instruction cache;
• an instruction dispatch stage coupled to both the instruction cache and the plurality of instruction buffers;
• an instruction issue stage coupled to the instruction dispatch stage;
• a dependency checking logic coupled to the instruction issue stage for identifying a dependent instruction following at least one long latency instruction with register dependencies from the first thread;
• the dependency checking logic for recycling the dependent instruction by providing the dependent instruction to an earlier pipeline stage;
• the dependency checking logic for delaying the dependent instruction at dispatch;
• the dependency checking logic for detecting completion of the at least one long latency instruction from the first thread;
• and
• the dependency checking logic for allowing the alternate thread to issue the one or more instructions while the at least one long latency instruction is being executed.

An in-order multithreading processor having two or more threads, comprising:

• means for identifying a dependent instruction following at least one long latency instruction with register dependencies from a first thread;
• means for recycling the dependent instruction by providing the dependent instruction to an earlier pipeline stage;
• means for delaying the dependent instruction at dispatch;
• means for detecting completion of the at least one long latency instruction from the first thread;
• and
• means for allowing an alternate thread to issue one or more instructions while the at least one long latency instruction is being executed.

A computer program product for improving throughput of an in-order multithreading processor, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:

• computer program code for identifying a dependent instruction following at least one long latency instruction with register dependencies from the first thread;
• computer program code for recycling the dependent instruction by providing the dependent instruction to an earlier pipeline stage;
• computer program code for delaying the dependent instruction at dispatch;
• computer program code for detecting completion of the at least one long latency instruction from the first thread;
• and
• computer program code for allowing the alternate thread to issue one or more instructions while the at least one long latency instruction is being executed.