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US 2004/0111592 A1Published application
Microprocessor performing pipeline processing of a plurality of stages
AssigneeRenesas Technology Corp.
InventorsChuma Nagao, Hiroshi Ueki
Life of this patent
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Abstract
A microprocessor is provided with two queue buffers, one for storing prefetched non branch instructions and the other for storing prefetched branch target instructions, and a plurality of process stages. The process stages are divided into one last process stage and other process stages those form two different paths. Non branch instructions are processed in one path and branch target instructions are processed in other path. The paths are changed based on whether branch condition is met or not.
Claims6
A microprocessor comprising:
- a memory for storing instructions;
- a first queue buffer and a second queue buffer, wherein the first queue buffer stores non branch instructions from among the instructions prefetched from the memory and the second queue buffer stores branch target instructions from among the instructions prefetched from the memory;
- a plurality of process stages that perform pipeline processing, wherein the process stages prior to a last process stage being arranged in a first path and a second path;
- a first changeover unit that judges if a branch condition of a branch instruction is met or not and, based on the judgment outcome selects any one of the first path and the second path for pouring the contents to the last process stage;
- a second changeover unit that, based on the judgment outcome, switches the connection of the first queue buffer and the second queue buffer with the first path and the second path.
2 more elements
Dependencies are inferred from the claim text.