Asynchronous multiple-order issue system architecture
AssigneeFulcrum Microsystems Inc. A California corporation
InventorsAndrew Lines, Robert Southworth, Uri Cummings
Life of this patent
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Abstract
An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
Claims49
An asynchronous circuit for processing units of data having a program order associated therewith, the circuit comprising an N-way-issue resource comprising N parallel pipelines, each pipeline being operable to transmit a subset of the units of data in a first-in-first-out manner, wherein the asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
A heterogeneous system for processing units of data having a program order associated therewith, the system comprising an N-way issue resource and at least one multiple-issue resource having an order different from N, the system further comprising interface circuitry operable to facilitate communication between the N-way-issue resource and the at least one multiple-issue resource and to preserve the program order in all of the resources.
Dependencies are inferred from the claim text.