System and method for managing a cache memory
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.
Claims51
A method for moving a data string within a cache memory system, the method comprising:
- reading a cache line from a data cache, the cache line containing at least a portion of a data string and having a starting source address;
- shifting the cache line a selected amount;
- storing the shifted cache line in a first destination cache line in the data cache, the shifted cache line having a starting destination address;
- and
- modifying a cache tag value associated with the first destination cache line to reflect a location of the data string in a main memory.
A cache memory system for moving a data string, the cache memory system comprising:
- a cache memory comprising:
- a cache data memory configured to store a data string;
- and
- a cache tag memory associated with the cache data memory;
- and
- a shifter coupled to the cache memory, the shifter being configured to shift an entire cache line containing at least a portion of the data string in a single processor cycle, the cache data memory being configured to store the shifted cache line in a destination cache line.
A method of reassigning data from a first memory location to a second memory location comprising:
- reading a cache line containing at least a portion of a data string from a data cache;
- shifting the cache line a selected amount;
- and
- storing the shifted cache line in the data cache.
23 The method of claim 22, wherein a capacity of the register is less than the size of the cache line.
A cache memory comprising:
- a data memory;
- and
- a barrel shifter coupled to the data memory, the barrel shifter being configured to shift an entire cache line in a single processor cycle.
A processor comprising:
- a cache memory;
- means for reading a cache line from the cache memory;
- means for shifting the cache line a selected amount;
- means for storing data shifted out of the cache line;
- and
- write circuitry for writing the shifted cache line to the cache memory.
Dependencies are inferred from the claim text.