Causality-based memory ordering in a multiprocessing environment

An apparatus comprising:

• a plurality of processors;
• access optimization buffering circuitry;
• causality monitoring logic to monitor causal relationships with respect to observed stores;
• and
• arbitration logic coupled with the causality monitoring logic and said access optimization buffering circuitry and to allow a plurality of stores generated in a first order of stores by any two or more of the plurality of processors to be observed by at least one of said plurality of processors, wherein the observation indicates an order of stores different from said first order of stores.

A machine automated method comprising:

• receiving a plurality of stores generated in a first order of stores from a plurality of bus agents;
• allowing the plurality of stores to be observed by at least one other of said plurality of bus agents, said observation contradicting the first order of stores;
• dynamically determining if causality with respect to observed stores would be violated by allowing the plurality of stores to be observed contradictory with the first order of stores;
• and
• maintaining a processor consistency memory ordering model transparently to said plurality of bus agents.

A system comprising:

• a plurality of processors;
• store buffering circuitry to buffer stores received from at least one processor of the plurality of processors;
• causality monitoring logic coupled to said store buffering circuity, the causality monitoring logic to monitor, for said plurality of processors, causal relationships with respect to buffered stores;
• and
• store forwarding logic to forward data from a first store to a first memory location from a first one of said plurality of processors to a load of the first memory location from a second one of said plurality of processors if no causal relationship exists with respect to the first store and the second one of said plurality of processors.