High speed memory cloning facility via a coherently done mechanism

A method of completing a data move operation issued by a processor on a data processing system, said method comprising:

• issuing operations to a memory cloner that initiate a data clone operation;
• delaying execution of subsequent instructions in an instruction stream until a receipt of a signal from said memory cloner indicating the data clone operation is architecturally complete;
• receiving a signal from the memory cloner, wherein said signal is received when the data clone operation is architecturally completed while a physical move of the data is still in progress;
• and
• in response to receiving said signal, executing said subsequent instructions prior to completion of the physical move.

The processor operating method of claim 10, further comprising:

• issuing a series of naked write operations with no data;
• tracking a receipt of Null responses for each naked write operation of said series;
• and
• when all of said naked write operations receive a Null response, generating said signal sent to said processor indicating that the naked write operation has completed, wherein said processor does not distinguish from said signal indicating completion ofthe naked write in which no date is written and completion of an actual write in which the data is written.

A data processing system comprising:

• a processor chip with a processor and a high speed memory cloner;
• a memory coupled to said processor chip, said memory having a source memory location and a destination memory location;
• wherein said processor executes an instruction stream that includes instructions for completing a data clone operation and following instructions;
• and
• wherein said memory cloner includes means for signaling said processor to resume processing of the following instructions prior to a completion of the physical move of data to the destination memory location corresponding to the data clone operation.

The data processing system of claim 12, said memory clone further comprises:

• means for issuing a series of naked write operations to a destination address;
• means for tracking a receipt of Null responses for each naked write operation of said series;
• and
• when all of said naked write operations receive a Null response, means for generating a signal sent to said processor indicating that the naked write operation has completed, wherein said processor does not distinguish between a signal indicating completion of the naked write in which no data is written and completion of an actual write in which the data is written.

The data processing system of claim 12, said processor further comprising:

• means for issuing to a high speed memory cloner instructions that initiate a data clone operation;
• means for delaying execution of subsequent instructions until a receipt of an acknowledgment from said high speed memory cloner indicating the data clone operation has completed;
• means for receiving an acknowledgment from the memory cloner, wherein said acknowledgment received from said memory cloner only indicates that the data clone operation is architecturally completed, while an actual completion of the physical move operation is still in progress;
• and
• means, responsive to a receipt ofthe acknowledgment, for immediately resuming execution of said subsequent instructions.