Distributed result system for high-performance wide-issue superscalar processor
AssigneeLSI Logic Corporation
InventorHung T. Nguyen
Life of this patent
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Abstract
A system for handling distributed results in a high-performance wide-issue superscalar processor having result-forwarding capability is disclosed. The system generally includes buffer logic configured to produce write data and write information to a register file. The register file generally has a plurality of registers and is adapted to receive the write information, the write data, and read information. The register file also includes logic configured to produce the write data as read data output when the read information and the write information specify the same register. An embodiment of the disclosed register file includes multiple registers for storing data, read logic, correction logic, and muxing logic.
Claims32
A register file system, comprising:
- a plurality of registers for storing data;
- read logic adapted to receive read information specifying one of the registers, wherein the read logic is configured to access the register specified by the read information and to produce data obtained from the register specified by the read information as read data;
- write logic adapted to receive write information and corresponding write data, wherein the write logic is configured to store the write data in the register specified by the write information;
- correction logic configured to produce the write data as read data output when the read information and the write information specify the same register.
A processor, comprising:
- a functional unit configured to perform at least one function of the processor;
- a register file coupled to the functional unit, comprising:
- a plurality of registers for storing data;
- read logic coupled to receive read information specifying one of the registers, and wherein the read logic is configured to access the register specified by the read information and to produce data obtained from the register specified by the read information as read data;
- correction logic coupled to receive:
- (i) the read information, and (ii) write data and corresponding write information from the at least one functional unit, wherein the write information specifies one of the registers, and wherein the correction logic is configured to produce the write data as correction data, and wherein the correction data is valid when the register specified by the write data is the same register specified by the read information;
- and
- muxing logic coupled to receive the read data from the read logic and the correction data from the correction logic, and configured to produce the read data as read data output when the correction data is not valid.
A processor, comprising:
- buffer logic configured to produce write data and corresponding write information;
- and
- a register file comprising a plurality of registers and adapted to receive:
- (i) read information, and (ii) the write data and the corresponding write information, wherein the read information and the write information both specify one of the registers, and wherein the register file comprises logic configured to produce the write data as read data output when the read information and the write information specify the same register.
A method for operating a register file, comprising:
- receiving:
- (i) read information, and (ii) write data and corresponding write information, wherein the read information and the write information both specify one of a plurality of registers of the register file;
- and
- producing the write data as read data output when the read information and the write information specify the same register.
Dependencies are inferred from the claim text.