Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors
OwnerSamantha J. Edirisooriya, Sujat Jamil +4inventors
InventorsSamantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen
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Abstract
A system and method for improved cache performance is disclosed. In one embodiment, cache coherency schemes are categorized by whether or not they are capable of write-back caching. A signal may convey this information among the processors, allowing them to inhibit snooping in certain cases. In another embodiment, backoff signals may be exchanged among the processors, permitting them to inhibit certain unnecessary data transfers on a system bus.
Claims33
An agent, comprising:
- a cache memory;
- and
- a bus interface coupled to said cache memory and to a bus, including an ownership capable interface to said bus, wherein said ownership capable interface is to communicate a ownership capability status when said cache initiates a write-line transfer.
A method, comprising:
- initiating a write-line transaction from a first agent;
- communicating an ownership capability status of said first agent over a bus;
- determining whether a second agent should perform a cache snoop responsive to said ownership capability status.
A system, comprising:
- a first agent including a first cache and a first bus interface to a bus, wherein said first bus interface to drive an ownership capable status signal false when said first cache initiates a first write-line request;
- a second agent including a second cache and a second bus interface to said bus, wherein said second bus interface to drive said ownership capable status signal true when said second cache initiates a second write-line request;
- and
- a third agent with a third bus interface to said bus, wherein said third bus interface to drive said ownership capable status signal false when said third agent initiates a third write-line request.
An agent, comprising:
- a cache memory including a cache logic;
- a first backoff output signal coupled to said cache logic to indicate that said agent does not need a second agent to supply data for a first cache line;
- and
- a backoff input signal coupled to said cache logic to permit said cache memory to intervene with data for a second cache line if said backoff input signal is false.
A method, comprising:
- initiating a cache line write request for a first cache line in a first agent;
- performing a snoop to a first cache of said first agent;
- initiating a read and invalidate request in said first agent;
- and
- setting a first backoff output signal true if said first cache line is in a shared state.
A system, comprising:
- a bus;
- a first agent coupled to said bus, including a first cache, a first backoff output signal coupled to said first cache to indicate that said first cache does not need externally supplied data for a first cache line, and a first backoff input signal coupled to said cache to permit said cache to intervene with data for a second cache line if said backoff input signal is false;
- a memory controller coupled to said bus, including a second backoff input signal to permit said memory controller to intervene with data for a second cache line if said backoff input signal is false;
- and
- an audio input/output controller coupled via a bus bridge to said bus.
Dependencies are inferred from the claim text.