System and method for managing a cache memory
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.
Claims49
A cache memory comprising:
- a data memory configured to hold cache lines comprising a plurality of bytes of data;
- and
- a plurality of comparators, wherein each comparator has a first input coupled to said data memory such that each comparator receives one of said plurality of bytes of data via its associated first input, and wherein each comparator has a second input coupled to a second data source, such that the cache line may be compared to data received from the second data source.
A cache memory for comparing a data value with data in a cache memory, the cache memory comprising:
- a cache data memory configured to hold at least one cache line comprising a plurality of bytes of data;
- a data source configured to hold a data value, wherein the data value comprises fewer bytes than the cache line;
- a plurality of comparators configured to compare the cache line to the data value, each comparator having a first input coupled to said cache data memory and configured to receive at least one of said plurality of bytes of data, a second input coupled to the data source and configured to receive at least a portion of the data value from the data source, and an output;
- and
- a decoder coupled to the outputs of the plurality of comparators and configured to identify a portion of the cache line that matches at least a portion of the data value.
A method for comparing cache memory data in a digital processing system with a test data string, the method comprising:
- receiving an instruction to perform a compare operation, said instruction comprising a starting address and a test data string for said compare operation;
- routing the instruction to a data string manipulation circuit;
- routing the starting address for the compare operation from the data string manipulation circuit to a cache memory;
- comparing the test data string with cached data stored in a cache line of the cache memory, wherein said test data string comprises fewer bytes than the cache line;
- and
- routing an address of cached data matching the test data string to the data string manipulation circuit.
A method for comparing a string of data in a cache memory with a test data string, the method comprising:
- receiving an instruction to perform a compare operation, said instruction comprising a starting address for said compare operation;
- routing the instruction to a data string manipulation circuit;
- routing the starting address for the compare operation from the data string manipulation circuit to a cache memory array;
- comparing a test data string with data stored in the cache memory array;
- and
- routing an address of cached data matching the test data string to the data string manipulation circuit.
A cache memory comprising:
- a data source means for storing a test data;
- a cache memory means for storing at least one cache line comprising a plurality of bytes of data;
- a means for comparing the test data with the plurality of bytes of data, the means for comparing coupled to the data source means and to the cache memory means;
- and
- a means for decoding coupled to the means for comparing, wherein the means for decoding identifies a portion of the cache line that matches at least a portion of the test data.
Dependencies are inferred from the claim text.