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US 2004/0111554 A1Published application
Flash memory with fast boot block access
AssigneeMicron Technology, Inc.
InventorsChristophe J. Chevallier, Allahyar Vahidimowlavi
Life of this patent
Estimating the term…
Abstract
A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.
Claims37
A flash memory device comprising:
- an array of addressable memory cells arranged in addressable blocks, the addressable blocks comprise a boot block and at least one additional memory cell block;
- a first address decoder circuit coupled to the boot block;
- a first voltage pump circuit coupled to the first address decoder circuit for providing a word line voltage signal to the boot block;
- a second address decoder circuit coupled to the additional memory cell block;
- and
- a second voltage pump circuit coupled to the second address decoder circuit for providing a word line voltage signal to the additional memory cell block.
3 more elements
A processing system comprising:
- a processor device;
- and
- a flash memory device coupled to the processor device via at least address and data buses, the flash memory device comprising,
- an array of addressable memory cells arranged in addressable blocks, the addressable blocks comprise a boot block and at least one additional memory cell block;
- a first address decoder circuit coupled to the boot block;
- a first voltage pump circuit coupled to the first address decoder circuit for providing a word line voltage signal to the boot block;
- a second address decoder circuit coupled to the additional memory cell block;
- and
- a second voltage pump circuit coupled to the second address decoder circuit for providing a word line voltage signal to the additional memory cell block.
6 more elements
A flash memory device comprising:
- an array of addressable memory cells arranged in addressable blocks, the addressable blocks comprise a first memory cell location and a second memory cell location;
- a first address decoder circuit coupled to the first memory cell location;
- and
- a second address decoder circuit coupled to the second memory cell location, such that the first and second memory cell locations have two different access times from activation of the flash memory device.
1 more element
Dependencies are inferred from the claim text.