Zone boundary adjustment for defects in non-volatile memories
AssigneeSanDisk Corporation
InventorKevin M. Conley
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AssigneeSanDisk Corporation
InventorKevin M. Conley
Estimating the term…
A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.
A memory system circuit, comprising:
A memory system circuit, comprising:
A method of operating a non-volatile memory system comprising a plurality of blocks of non-volatile storage elements wherein the storage elements within individual ones of the blocks are simultaneously erasable, and a memory controller circuit that controls programming of data into addressed blocks, reading data from addressed blocks and erasing data from one or more of addressed blocks at a time wherein the non-volatile storage elements are organized by the controller into logical zones each comprised of one or more blocks for address translation, the method comprising:
A method of operating a non-volatile memory system comprising a plurality of blocks of non-volatile storage elements wherein the storage elements within individual ones of the blocks are simultaneously erasable, and a memory controller circuit that controls programming of data into addressed blocks, reading data from addressed blocks and erasing data from one or more of addressed blocks at a time wherein the non-volatile storage elements are organized by the controller into logical zones each comprised of one or more blocks for address translation, the method comprising:
A memory system circuit, comprising:
Dependencies are inferred from the claim text.