US 2004/0111551 A1Published application

Process for emulating associative memory

AssigneeBull HN Information System Inc.

InventorBruce A. Noyes

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Abstract

A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit incrementable validity counter. The target associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the target processor when access to a given page in main memory is sought. Each entry in the target associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. The target multi-digit counter stores a current validity count. When access to a data page is sought, comparisons are made: 1) between the high order virtual address component of the data page and the high order virtual address component read from the target associative memory entry; and 2) between the multi-digit validity count read from the target associative memory entry and the multi-digit current validity count in the target counter. If there is a full match, the real page address of the requested page is read from the target associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the target associative memory is updated accordingly.

Claims26

Dependent claims

In a host computer system including a host processor, a host memory and an addressable main memory coupled to the host processor, the main memory storing data pages, at least one data page storing a page table, a process, carried out by the host computer system, for emulating a target computer system running target system software comprising:

A) establishing a representation of a target system processor in the host memory;
B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding:
1) a high order virtual address component;
2) a real page address;
and
3) a multi-digit validity count;
C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count;
D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested:
1) using a low order virtual address component of the requested data page to specify an entry in the target system associative memory;
2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry;
and
3) comparing the multi-digit validity count read from the specified target system associative memory entry to the multi-digit current validity count in the target system counter;
E) if there are matches:
1) between the requested high order virtual address component and the high order address component read from the target system associative memory;
and
2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory;
then concatenating the real page address in the specified entry in the target system associative memory with an appended offset value to access a main memory block in the requested data page in main memory;

14 more elements

A) establishing a representation of a target system processor in the host memory;
B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries in multiple levels of association, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding:
1) a high order virtual address component;
2) a real page address;
and
3) a multi-digit validity count;
C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count;
D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested:
1) using a low order virtual address component of the requested data page to specify an entry at each level of association in the target system associative memory;
2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry at each level of association;
and
3) comparing the multi-digit validity count read from the specified target system associative memory entry at each level of association to the multi-digit current validity count in the target system counter;
E) if there are matches:
1) between the requested high order virtual address component and the high order address component read from the target system associative memory at one level of association;
and
2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory at the one level of association;
using the real address in the specified entry in the target system associative memory at the one level of association to access the requested data page in main memory.

14 more elements

A) establishing a representation of a target system processor in the host memory;
B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding:
1) a high order virtual address component;
2) a real page address;
and
3) a multi-digit validity count;
C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count;
D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested:
1) using a low order virtual address component of the requested data page to specify an entry in the target system associative memory;
2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry;
and
3) comparing the multi-digit validity count read from the specified target system associative memory entry to the multi-digit current validity count in the target system counter;
E) if there are matches:
1) between the requested high order virtual address component and the high order address component read from the target system associative memory;
and
2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory;
then concatenating the real page address in the specified entry in the target system associative memory with an appended offset value to access a main memory block in the requested data page in main memory;
G) if there is a no-match condition in at least one of steps E)1) and E)2):
1) accessing the page table stored in the main memory to obtain the real page address of the requested data page identified by the high order and low order virtual address components thereof;
and
2) concatenating the real page address obtained from the page table with an appended offset value to access a main memory block in the requested data page in main memory;
and
3) updating the entry in the target system associative memory specified by the low order virtual address of the requested data page by placing:
a) the high order virtual address component for the requested data page, as obtained from the page table, into the high order virtual address component field of the specified entry;
b) the real page address for the requested data page, as obtained from the page table, into the real page address field of the specified entry;
and
c) the current count in the target system multi-digit counter into the multi-digit validity count field of the specified entry;
and;
H) selectively incrementing the target system multi-digit counter to simultaneously invalidate all entries in the target system associative memory.

26 more elements

A) establishing a representation of a target system processor in the host memory;
B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries in multiple levels of association, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding:
1) a high order virtual address component;
2) a real page address;
and
3) a multi-digit validity count;
C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count;
D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested:
1) using a low order virtual address component of the requested data page to specify an entry at each level of association in the target system associative memory;
2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry at each level of association;
and
3) comparing the multi-digit validity count read from the specified target system associative memory entry at each level of association to the multi-digit current validity count in the target system counter;
E) if there are matches:
1) between the requested high order virtual address component and the high order address component read from the target system associative memory at one level of association;
and
2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory at the one level of association;
concatenating the real page address in the specified entry in the target system associative memory at the one level of association with an appended offset value to access a main memory block in the requested data page in main memory;
G) if there is a no-match condition in at least one of steps E)1) and E)2):
1) accessing the page table stored in the main memory to obtain the real page address of the requested data page identified by the high order and low order virtual address components thereof;
and
2) concatenating the real page address obtained from the page table with an appended offset value to access a main memory block in the requested data page in main memory;
and
3) updating the entry in the target system associative memory specified by the low order virtual address of the requested data page by placing:
a) the high order virtual address component for the requested data page, as obtained from the page table, into the high order virtual address component field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page;
b) the real page address for the requested data page, as obtained from the page table, into the real page address field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page;
and
c) the current count in the target system multi-digit counter into the multi-digit validity count field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page;
and
H) selectively incrementing the target system multi-digit counter to simultaneously invalidate all entries in the target system associative memory.

26 more elements

Dependencies are inferred from the claim text.