High speed memory cloning facility via a lockless multiprocessor mechanism
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Benjiman Lee Goodman, Jody Bern Joyner
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AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Benjiman Lee Goodman, Jody Bern Joyner
Estimating the term…
A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.
A processing unit comprising:
A method for enabling dynamic, software selection of an interrupt mode of a data processing system that includes at least one processor that issues instructions on an external fabric of said data processing system, said method comprising:
A multiprocessor data processing system, comprising:
A multiprocessor data processing system comprising:
Dependencies are inferred from the claim text.