Hybrid arithmetic logic unit
AssigneeMicron Technology, Inc.
InventorJon Skull
Life of this patent
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Abstract
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.
Claims44
An arithmetic logic unit (ALU), comprising:
- a first adder operative to receive a first and second input and operative to generate a first output and a second output;
- a first register coupled to receive and store said first output, said first register coupled to provide stored register contents to said first input;
- a second register coupled to receive and store said second output, said second register coupled to provide stored register contents to said second input;
- and
- a second adder coupled to receive said first output and said second output, said second adder operative to generate a result based on said first and second outputs.
A method of performing arithmetic operations in a computer processor, said method comprising:
- generating a sum result and a carry result in a first clock cycle based on first, second, and third inputs, said sum result being a bitwise summation not including any carries and said carry result including carries generated by said bitwise summation;
- storing said sum result and said carry result;
- feeding back said stored sum and carry results to said first and said second inputs, respectively, during an immediately subsequent clock cycle;
- and
- adding said sum and carry results in a clock cycle after said first clock cycle.
A data processing system comprising:
- a memory;
- and
- a processor coupled to said memory, said processor comprising an arithmetic logic unit, said arithmetic logic unit comprising:
- a first adder that generates two output signals per clock cycle based on at least two input signals;
- at least two registers that respectively receive said output signals, said at least two registers feeding said output signals back to said first adder during a subsequent clock cycle;
- and
- a second adder coupled to said first adder, said second adder completing an arithmetic operation partially executed by said first adder within at least one additional clock cycle.
A printed circuit board comprising an arithmetic logic unit mounted thereon, said arithmetic logic unit comprising:
- a first adder that generates a sum and carry per clock cycle based on at least two inputs, said sum not including any carries generated by said first adder;
- two registers that respectively receive said sum and carry, said registers feeding said sum and carry back to said first adder during a subsequent clock cycle;
- and
- a second adder that receives said sum and carry from said first adder, said second adder completing an arithmetic operation partially completed by said first adder in a clock cycle immediately subsequent to the clock cycle in which said sum and carry were generated.
An arithmetic logic unit comprising:
- a first adder that generates partial results of an arithmetic operation in one clock cycle;
- feedback circuitry that provides said partial results back to said first adder for use in another operation;
- and
- a second adder that generates a complete result in one or more clock cycles based on said partial results.
A method of performing arithmetic operations in a computer processor, said method comprising:
- generating two partial results from a bitwise summation of at least two inputs in one clock cycle;
- storing said two partial results;
- and
- generating a final result based on said two partial results in at least one clock cycle.
Apparatus for performing arithmetic operations in a computer processor, said apparatus comprising:
- means for generating two partial results from a bitwise summation of at least two inputs in one clock cycle;
- means for storing said two partial results;
- and
- means for generating a final result based on said two partial results in at least one clock cycle.
An arithmetic logic unit comprising:
- first adder means for receiving a first, second, and third input and for generating a first output and a second output;
- first register means for storing said first output;
- second register means for storing said second output;
- and
- second adder means for receiving said first and second outputs and for generating a result based on said first and second outputs.
An arithmetic logic unit comprising:
- a first adder that generates first and second partial results in a same clock cycle;
- a second adder that generates first and second alternative partial final results in a same clock cycle based on a portion of said first partial result and a portion of said second partial result;
- a multiplexor that receives said first and second alternative partial final results, said multiplexor outputting one of said first and second alternative results;
- and
- a third adder that generates a sum based on the remaining portions of said first and second partial results.
Dependencies are inferred from the claim text.