Optimization of timing models using bus compression

The method as recited in Claim 2 further comprising the steps of:

• g1) calculating a figure of merit using said timing information for said third transistor-level timing arc and said bounding timing information when said timing information for said third transistor-level timing arc is greater than said bounding timing information;
• g2) comparing said figure of merit from said step gl) to said specified acceptance value;
• g3) grouping said third transistor-level timing arc with said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit from said step gl) is acceptable;
• g4) revising said bounding timing information for said compressed transistor-level timing arc using said timing information for said third transistor-level timing arc;
• and
• g5) representing said first, second and third transistor-level timing arcs by said compressed transistor-level timing arc.

n a circuit timing model, a method of compressing bus-related model data for transistor-level timing arcs having a plurality of start nodes coupled to a common end node, said method comprising the computer-implemented steps of:a) comparing timing information for a first transistor-level timing arc and timing information for a second transistor-level timing arc having consecutive start nodes on a first bus and a common end node on a second bus;b) calculating a figure of merit using said timing information for said first transistor-level timing arc and said timing information for said second transistor-level timing arc,

• wherein said figure of merit is one of:
• a difference between a first timing information associated with the first transistor-level timing arc and a second timing information associated with the second transistor-level timing arc;
• and
• a ratio between the first timing information associated with the first transistor-level timing arc and the second timing information associated with the second transistor-level timing arc;
• c) comparing said figure of merit to a specified acceptance value;
• d) grouping said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit is acceptable;
• ande) in a compressed circuit model, representing said first transistor-level timing arc and said second transistor-level timing arc by a compressed transistor-level timing arc, wherein said timing information for said first transistor-level timing arc and said timing information for said second transistor-level timing arc determine bounding timing information for said compressed transistor-level timing arc.

The method as recited in Claim 11 further comprising the steps of:

• gl) calculating a figure of merit using said timing information for said third transistor-level timing arc and said bounding timing information when said timing information for said third transistor-level timing arc is greater than said bounding timing information;
• g2) comparing said figure of merit from said step gl) to said specified acceptance value;
• g3) grouping said third transistor-level timing arc with said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit from said step gl) is acceptable;
• g4) revising said bounding timing information for said compressed transistor-level timing arc using said timing information for said third transistor-level timing arc;
• and
• g5) representing said first, second and third transistor-level timing arcs by said compressed transistor-level timing arc.

In a circuit timing model, a method of compressing bus-related model data for transistor-level timing arcs having a common start node coupled to a plurality of end nodes, said method comprising the computer-implemented steps of:a) comparing timing information for a first transistor-level timing arc and timing information for a second transistor-level timing arc having a common start node on a first bus and consecutive end nodes on a second bus;b) calculating a figure of merit using said timing information for said first transistor-level timing arc and said timing information for said second transistor-level timing arc,

• wherein said figure of merit is one of:
• a difference between a first timing information associated with the first transistor-level timing arc and a second timing information associated with the second transistor-level timing arc;
• and
• a ratio between the first timing information associated with the first transistor-level timing arc and the second timing information associated with the second transistor-level timing arc;
• c) comparing said figure of merit to a specified acceptance value;
• d) grouping said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit is acceptable;
• ande) in a compressed circuit model, representing said first transistor-level timing arc and said second transistor-level timing arc by a compressed transistor-level timing arc, wherein said timing information for said first transistor-level timing arc and said timing information for said second transistor-level timing arc determine bounding timing information for said compressed transistor-level timing arc.

The method as recited in Claim 18 further comprising the steps of:

• gl) calculating a figure of merit using said timing information for said third transistor-level timing arc and said bounding timing information when said timing information for said third transistor-level timing arc is greater than said bounding timing information;
• g2) comparing said figure of merit from said step gl) to said specified acceptance value;
• g3) grouping said third transistor-level timing arc with said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit from said step gl) is acceptable;
• g4) revising said bounding timing information for said compressed transistor-level timing arc using said timing information for said third transistor-level timing arc;
• and
• g5) representing said first, second and third transistor-level timing arcs by said compressed transistor-level timing arc.

A computer system comprising:an address/data bus;a processor coupled to said address/data bus;a computer-readable memory unit coupled to said address/data bus;said processor for performing a method of compressing bus-related model data for a plurality of transistor-level timing arcs, said method comprising the steps of:a) comparing timing information for a first transistor-level timing arc and timing information for a second transistor-level timing arc;b) calculating a figure of merit using said timing information for said first transistor-level timing arc and said timing information for said second transistor-level timing arc,

• wherein said figure of merit is one of:
• a difference between a first timing information associated with the first transistor-level timing arc and a second timing information associated with the second transistor-level timing arc;
• and
• a ratio between the first timing information associated with the first transistor-level timing arc and the second timing information associated with the second transistor-level timing arc;
• c) comparing said figure of merit to a specified acceptance value;
• d) grouping said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit is acceptable;e) in a compressed circuit model, representing said first transistor-level timing arc and said second transistor-level timing arc by a compressed transistor-level timing arc, wherein said timing information for said first transistor-level timing arc and said timing information for said second transistor-level timing arc determine bounding timing information for said compressed transistor-level timing arc;
• andf) in said compressed circuit model, representing a third transistor-level timing arc by said compressed transistor-level timing arc when timing information for said third transistor-level timing arc is less than or equal to said bounding timing information.

The method as recited in Claim 24 further comprising the steps of:

• gl) calculating a figure of merit using said timing information for said third transistor-level timing arc and said bounding timing information when said timing information for said third transistor-level timing arc is greater than said bounding timing information;
• g2) comparing said figure of merit from said step gl) to said specified acceptance value;
• g3) grouping said third transistor-level timing arc with said first transistor-level timing arc and said second transistor-level timing arc when said figure of merit from said step gl) is acceptable;
• g4) revising said bounding timing information for said compressed transistor-level timing arc using said timing information for said third transistor-level timing arc;
• and
• g5) representing said first, second and third transistor-level timing arcs by said compressed transistor-level timing arc.