Method of optimizing signal lines within circuit, optimizing apparatus, recording medium having stored therein optimizing program, and method of designing circuit and recording medium having stored therein program for designing circuit

An apparatus for optimizing signal distribution through signal lines which connect a signal supplying source and a plurality of elements which are supplied with a signal from the signal supplying source through the signal lines, the apparatus being utilized when designing a circuit including the signal supplying source and the plurality of elements, the apparatus for optimizing the signal lines within the circuit, comprising:

• a determining unit (541) for determining whether or not the signal supplying source satisfies a fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source;
• a dividing unit (543) for dividing the plurality of elements into a plural number of groups so that the fan-out restriction is satisfied in each of the groups and that each of the groups has the same or substantially the same load capacity, when the determining unit (541) determines that the signal supplying source does not satisfy the fan-out restriction;
• and
• a buffer inserting unit (544) for inserting a buffer element having a size which makes the groups of elements satisfy the fan-out restriction, into each of the groups divided by the dividing unit (543);
• wherein
• the determining unit (541) regards the buffer element inserted by the buffer inserting unit (544) as a driven element and determines whether or not the signal supplying source satsifies the fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source, and
• the dividing unit (543) and the buffer inserting unit (544) repeat the processing thereof until the determining unit (541) delivers a determination that the signal supplying source satisfies the fan-out restriction.

A recording medium having an optimizing program stored therein, the program being utilized when designing a circuit including a signal supplying source and a plurality of elements which are supplied with a signal from the signal supplying source through signal lines, the program being executed by a computer (540) for optimizing signal distribution through the signal lines connecting the signal supplying source to each of the plurality of elements,

• the optimizing program comprising the procedures of:
• a procedure of determining whether or not the signal supplying source satisfies a fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source;
• a procedure of dividing the plurality of elements into a plural number of groups so that the fan-out restriction is satisfied in each of the groups and that each of the groups has the same or substantially the same load capacity, when it is determined in the determining procedure that the signal supplying source does not satisfy the fan-out restriction;
• and
• a procedure of inserting a buffer element having a size which makes the groups of elements satisfy the fan-out restriction, into each of the groups divided at the dividing procedure;
• wherein
• the buffer element inserted at the buffer inserting procedure is regarded as a driven element, and then it is again determined in the determining procedure whether or not the signal supplying source satisfies the fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source, and
• the computer (540) repeatedly carries out the dividing procedure and the buffer inserting procedure until the determining procedure delivers a determination that the signal supplying source satisfies the fan-out restriction.

A method of designing a circuit having a clock signal supplying source and a plurality of flip-flop cells which are supplied with a clock signal from the clock signal supplying source, the method for designing the circuit, comprising:

• a step (S111) of synthesizing logic of circuit designing contents described in a register transfer level so as to create a first netlist which regulates a connection relationship between the flip-flop cells constituting a circuit to be designed;
• a step (S112, S113) of executing a floorplan by using the first netlist so as to create a clock tree of the circuit to be designed, and creating a second netlist containing one or more buffer cells for driving the flip-flop cells based on the clock tree;
• a step (S122) of arranging a clock layout of the circuit to be designed based on floorplan information and the second netlist obtained by executing the floorplan so that the clock layout contains an initial placement of the buffer cells, the flip-flop cells, and clock signal lines connecting the one or more buffer cells and the flip-flop cells;
• and
• a step (S13) of effecting an ordinary net wiring except for the clock signal lines after arranging the clock layout, wherein
• in the initial placement, a number of buffer stages is adjusted so that each of the circuit path extending from the clock signal supplying source to the flip-flop cells consists of the same number of buffer stages.

A recording medium having stored therein a program for forcing a computer to aid in designing a circuit having a clock signal supplying source and a plurality of flip-flop cells which are supplied with a clock signal from the clock signal supplying source, the program forcing the computer to carry out sequentially the following steps comprising:

• a step (S111) of synthesizing logic of circuit designing contents described in a register transfer level so as to create a first netlist which regulates a connection relationship between the flip-flop cells constituting a circuit to be designed;
• a step (S112, S113) of executing a floorplan by using the first netlist so as to create a clock tree of the circuit to be designed, and creating a second netlist containing one or more buffer cells for driving the flip-flop cells based on the clock tree;
• a step (S122) of arranging a clock layout of the circuit to be designed based on floorplan information and the second netlist obtained by executing the floorplan so that the clock layout contains an initial placement of the buffer cells, the flip-flop cells, and clock signal lines connecting the one or more buffer cells and the flip-flop cell;
• and
• a step (S13) of effecting an ordinary net wiring except for the clock signal lines after arranging the clock layout, wherein
• in the initial placement the program causes the computer to adjust a number of buffer stages so that each of the circuit paths extending from the clock signal supplying source to the flip-flop cells consists of the same number of buffer stages.