Built-in self test circuit for integrated circuits

A configurable, built-in self-test circuit for testing an integrated circuit in cooperation with a data processor, the integrated circuit including a collection of addressable elements, the built-in self-test circuit comprising:

• an address generator that generates sequences of addresses identifying elements in the collection, the address generator including a plurality of registers that store scan pattern definition parameters defining a pattern of generation of the sequence of addresses;
• and
• a write/read controller coupled to the address generator and including:
• a data buffer that stores test data for testing the integrated circuit;
• a controller that transmits the test data and sequence of addresses to the integrated circuit for testing;
• and
• an evaluation circuit that receives and evaluates test results from the integrated circuit and modifies the test data stored in the data buffer in response to evaluating the test results.