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US 2004/0107394 A1Published application
IP core design supporting user-added scan register option
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
Claims14
An integrated circuit comprising:
- a. an intellectual property core free of any boundary scan register;
- and
- b. a test access port formed in the core, the test access port including test port interface signal leads and additional test input, test output and test control signal leads.
A process of executing boundary scan instructions at a test access port comprising:
- a. sensing that the external register present signal is in a logical condition indicating the absence of a user-added boundary scan register;
- and
- b. causing all boundary scan instructions to default to a bypass instruction.
A process of determining the presence of a user-added scan register comprising:
- a. capturing a logical state of an external register present signal in a shift register;
- b. shifting the contents of the shift register cut of the shift register;
- and
- c. examining the logical state of the external register present signal in the contents of the shift register shifted out of the shift register.
1 more element
Dependencies are inferred from the claim text.